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Manual Xilinx UG018

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  • Xilinx UG018 - page 1

    R PowerPC™ 405 Processor Block Reference Guide Embedded Development Kit UG018 (v2.0) August 20, 2004 ...

  • Xilinx UG018 - page 2

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com UG0 1 8 (v2.0) August 20 , 2004 1-800- 255-7778 "Xilinx" and t he Xilinx logo sho wn abov e are regis tered trademar ks of Xil inx, Inc. Any rights no t expre ssly gra nted herei n are reserved. CoolRunner , Rocke t Chips , Rocket IP , S partan, S t a teBENCH, S tate ...

  • Xilinx UG018 - page 3

    UG018 (v 2. 0) Aug ust 20, 2004 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 PowerPC™ 405 Processor Block Ref erence Guide UG018 (v2.0) August 20, 2004 The following table shows the revision hist ory for this documen t. V ersion Revision 09/16 /02 1.0 Initi al Emb e dde d D eve lop ment K it (E DK) rele as ...

  • Xilinx UG018 - page 4

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com UG0 1 8 (v2.0) August 20 , 2004 1-800- 255-7778 ...

  • Xilinx UG018 - page 5

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 5 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Reso urces . . . . . . . . . . . . . . . . . . . ...

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    6 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 R Instruction-Side PLB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Instruction-Side PLB I /O Signal Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx UG018 - page 7

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 7 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R ISOCM Controller In struction Fetch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 DSOCM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx UG018 - page 8

    8 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 R FCM Store Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 FCM Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx UG018 - page 9

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 9 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Pr efac e About This Guide This guide serves as a technical reference describing the har dware interface to the PowerPC ® 405 processor block. It con tains inform a tion on inpu t/output sign als , timing relationships betwe ...

  • Xilinx UG018 - page 10

    10 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Preface: About This Guide R Addi tiona l Resour ces For additiona l in formation, go to http:// support.xilinx.com . The follo win g table lists some of the resources you can access fr om thi s website. Y ou can also directly acce ...

  • Xilinx UG018 - page 11

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 11 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Online Docu ment The following conventions ar e us ed in thi s document: Helve tica bold Comman ds that you select from a men u Fil e o Ope n Key b oa r d short cu t s Ctrl+C Italic font V ariables in a syn tax statement for ...

  • Xilinx UG018 - page 12

    12 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Preface: About This Guide R General Conventions Ta b l e 1 - 1 lists th e genera l notational conv entions used througho ut thi s document. Registers Ta b l e 1 - 2 lists the PowerPC 405 registers used in this document and their d ...

  • Xilinx UG018 - page 13

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 13 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Te r m s TCR T im er - c on trol r egi ster TSR T imer-status register T able 1-2: PowerP C 405 Reg isters (Continued) Register Descrip tive Name acti ve As applied to sig nals, this term indica tes a signal is in a state th ...

  • Xilinx UG018 - page 14

    14 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Preface: About This Guide R exception An abnormal event or condition that requires the pr ocessor ’s attention. They can be caused by instr u ction execution or an external device. The pr ocessor records the occurr ence of an ex ...

  • Xilinx UG018 - page 15

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 15 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R OEA The PowerPC operating-enviro n ment architectur e, which defines the memory-manageme nt model, supervisor -level registers and instructions, syn chronization requirements, the exception model, an d th e time-base resour ...

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    16 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Preface: About This Guide R UISA The PowerPC user instruction-set a rchitectur e, which defin es the base user-level i nst ruction set, registers , da ta types, the memory model, the programm in g model, and the exception model as ...

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    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 17 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Chapter 1 Intr oduction to the PowerPC 405 Pr ocessor The PowerPC 405 is a 32-bit implementation of the PowerPC em bedded -environment arch ite ctur e th at is derived from the PowerPC architecture. Specifically , th e Power ...

  • Xilinx UG018 - page 18

    18 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R The PowerPC architectur e r equires that all PowerPC implementations adhere to the UISA, offering compatibility a mong all PowerPC applicat ion programs. However , dif feren ...

  • Xilinx UG018 - page 19

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 19 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R x Special-purpose r eg isters for controlling the use of debug res ou rces, timer resour ces, interrupts, real-mode storage attributes, memory- m anagem ent facilities, an d other architected pr o cessor r esour ces . x A de ...

  • Xilinx UG018 - page 20

    20 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R T able 1-2: OEA Features of the Pow e rPC Embedded-Env ironment Architecture Operating Environment Feat ur es Register model x Privileged special- purpos e registers (SPRs) ...

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    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 21 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R PowerPC 405 Sof tware Featu res The PowerPC 405 pro cessor core is an implementation of the PowerPC embedded- environment ar chitecture. The proces s or pr ovides fixed-point embedded applications with high performanc e at l ...

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    22 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R i W rite-ba ck and write-through support i Programmable load and store cache line allocati on i Operand forwarding during ca che line fills i Non-block ing during cache line ...

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    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 23 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Real Mode In rea l mo de , programs address physical memory directly . Virt ual Mode In virtual mode , pr ograms address virtual memory and vi rtu al-memory a ddresses ar e translated by the pr oces sor into physi cal -memor ...

  • Xilinx UG018 - page 24

    24 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R General-Purpose Registers The processor contains thirty -two 3 2-bit gene ral-purp ose re gisters (GPRs), id entified as r 0 through r 31. The contents of the GPRs are read ...

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    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 25 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R S pecial-Pur pose Registers The proces s or contains a number of 32-bit special-p urpose regist ers (SPRs). SPRs provide access to additional processor resour ces, such as the co unt register , the lin k register , debug res ...

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    26 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R Central-Processin g Unit The PowerPC 405 central-processing unit (CPU) implements a 5-stage instruction pipeline consisting of fetch, decode, execute, write-back, and load w ...

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    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 27 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R read ports and two write ports. During the decode stage, d ata is read out o f the GPRs for use by the execute unit. During the write-back stage, re sults are w ritten to the GPR. The use of five r ead/write ports on the GPR ...

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    28 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R Software manages the in itia lization a nd replacement of TLB entries. The PowerP C 40 5 includes instru ction s for managing TLB entries by softwa re r un nin g in privileg ...

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    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 29 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R T imer Resources The PowerPC 405 contains a 64 -bit time base and thr ee timers. The time base is incremented synchronously using the CPU clock o r an external clock source. The three timers are incre m ented synchronously w ...

  • Xilinx UG018 - page 30

    30 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R x Device control re g ist er interface x Clock and powe r managem ent int erface x JT AG port interface x On-chip interrupt controller interface x On-chip memo ry controller ...

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    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 31 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R caches and the tim e as sociated w ith perf orm ing cache-line fills an d flushes. Unless st ated otherwise, the number of cycles described applies to systems ha ving zero-wait-state memory access. T able 1-3: PowerP C 405 C ...

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    32 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapt er 1: Introduction to t he PowerPC 405 Processor R ...

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    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 33 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Chapter 2 Input/Output Interfaces This chapt er describes all PowerPC 4 05 input/ou tput signal s associated w ith the foll owing processor block interfaces: x “Clock an d Power Management Interface” x “CPU Contr o l I ...

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    34 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Appendix B, “S ign al Summary ,” alpha betica lly lists the sig na ls d e scribed in this chapter . The l/O desig na tion and a descri ption summary a re included for each signal. Signal Na ...

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    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 35 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Clock an d Power Managem ent Interfa c e The clock and pow e r ma nagement (CPM) interf ace enables power-sensitive appl ications to control the processor clock using external logi c. The OCM con trollers ar e clo cked separ ...

  • Xilinx UG018 - page 36

    36 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R i The DBGC405D EBUGHAL T chi p-input sig nal (if provided) is asserted. Assert ion of this signal in dicates that an external debug tool w ants to control the PowerPC 405 pr ocessor . See “DB ...

  • Xilinx UG018 - page 37

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 37 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R CPM Interface I/ O Signal Descriptions The following sections describe the operation of the CPM interface I/O signals. CPMC405CLOCK (Input) This signal is th e source clock for all PowerPC 405 logi c (including timers). It i ...

  • Xilinx UG018 - page 38

    38 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R CPMC405TIMER TICK (Input) This signal is used to contr ol the update frequency of t he PowerPC 405 time base an d PIT (the FIT and WDT are timer events triggered by the time base). The time bas ...

  • Xilinx UG018 - page 39

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 39 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R C405CPMMSREE, C405CPMMSR C E, and C405CPMTIMERIR Q signals before using them to control the processor clocks. C405CPMTIMERIRQ (Output) When asserted, this signal indicates a timer exception occurred w it hin the PowerPC 405 ...

  • Xilinx UG018 - page 40

    40 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R x PLBCLK, primary PLB I/O Bus clock. x BRAMISOCMCLK, r efer ence clock for the I- Side OCM contro ller . x BRAMDSOCMCLK, r eferenc e clock for the D-Side OCM co ntroller . x CPMFCMCLK, refer e ...

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    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 41 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R clocks for the OCM cont rollers in the proce s sor block: BRAMDSOCMCLK (data side contr oller) and BRAMISOCMCLK (instr ucti on side contr ollers). The data side contr oller and the instruction side contr ollers can run at di ...

  • Xilinx UG018 - page 42

    42 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R CPU Control I nterface I/O Signal Descriptions The following sections describe the operatio n of the CPU control-interface I/O signals. TIEC405MMUEN (Input) When held active (tied to lo gic 1), ...

  • Xilinx UG018 - page 43

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 43 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R instructions foll owing the load require the loaded data. Dis abling operand forwa rding may improve the perform a n ce (clock fr equency) of the PowerPC 405. C405XXXMACHINECHECK (Output) When asserted, this signal indicates ...

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    44 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R JTGC405TR STNEG signal s for at least sixteen cl ock cycles. FPG A designers ca nnot mo dify the processor block power-on r eset mechanis m. The r es et logic is not requir ed to support all th ...

  • Xilinx UG018 - page 45

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 45 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Reset In ter f ace I/ O S i gna l D es cr ip tio n s The following sections describe the oper ation of the reset interfa c e I/O si gnals. C405RSTCORERESETREQ (Outpu t) When asserted, this signal indicates th e p rocessor bl ...

  • Xilinx UG018 - page 46

    46 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R RSTC405RESETSYS input to the pr ocessor block. When deasserted, no system-r eset request exists. U n like GSR, this output has no associated reset connectivity in the FPGA. The processor a s se ...

  • Xilinx UG018 - page 47

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 47 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Ta b l e 2 - 5 , p a g e 4 4 s hows the valid combinati ons of the RSTC405RES ETCORE , RSTC405RES ETCHIP , an d RSTC4 05RESETSYS s ignals and their ef f ect on the DBSR[MRR ] field followin g reset. JTGC405TRSTNEG (Input) Th ...

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    48 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R x The r equest priority is indicated by C405PLBICUPRIORITY[0:1]. See “C 405P LBI CUPR I OR I TY[0 :1] (O utp ut)” . The PLB arbiter uses this information to prioritize simu ltaneous request ...

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    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 49 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R placed in the ICU fill bu f f er , but not in the in struction cache. Subsequent in struction fetches fro m the same non-cacheable line are r ead from the fill buf fer ins tead of requiring a separate arbitration a nd transf ...

  • Xilinx UG018 - page 50

    50 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R x The pre fetch addr ess does not fall outside the curre nt 1 KB physical page. Addres s pipelining of cacheable prefetch re quests can occu r if all of the follo win g conditions are met: x Ad ...

  • Xilinx UG018 - page 51

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 51 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Instruct ion-Side PLB Interface I/O Signa l Descriptions The following sections describe the operatio n of the instructio n- side PLB interface I/O signals. Throughout these des criptions and un less otherwi se noted, the te ...

  • Xilinx UG018 - page 52

    52 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R C405PLBICUREQUEST (Output) When asserted, this signal indicates the ICU is requesting instr u ction s from a PLB slave device. The PLB s lave asserts PLBC405ICUAD DRACK to acknowledge the reque ...

  • Xilinx UG018 - page 53

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 53 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R C405PLBICUSIZE[2:3 ] (Output) These signals are u sed to specify the line-transfe r si ze of the instruction-fetch request. A four- w ord transfer siz e is specified when C405PLBICUSIZ E[2:3] 0b01. An eight-wor d transfer si ...

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    54 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R C405PLBICUU0A TTR (Output) This signal r eflects the value of the user-defined (U0) stora g e attribute for the tar get address . The requested instructions ar e not in mem ory locat ions chara ...

  • Xilinx UG018 - page 55

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 55 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R PLBC405ICUADDRACK (Input) When asserted, this signal indicates th e PLB slave acknowledges the ICU fetch request (indicated by the ICU assertion of C405PL BICUREQUEST). When deasserted, n o such acknowledgement exists. A fet ...

  • Xilinx UG018 - page 56

    56 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R x When a 64-bit PLB slave responds, an aligned doubleword is sent from the s lave to the ICU during each transf er cycl e. Both wor ds are r ead from the 64 -bit interface by the ICU in this cy ...

  • Xilinx UG018 - page 57

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 57 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R The ICU r eads either the low 32 bits or the high 32 bits of the 64-bit interfac e, depending on the value of PLBC405ICURDWDADDR[1:3]. x When a 64-bit PLB slave responds, an aligned doubleword is sent from the s lave to the ...

  • Xilinx UG018 - page 58

    58 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R transfer order is invalid if th is signal asserted. The en tries for a 32-bit PLB slave as sume the connection to a 64-bit master shown in Figure 2-5 , ab ove . PLBC405ICUBUSY ( Input) When ass ...

  • Xilinx UG018 - page 59

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 59 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Following reset, the processor block prevents the ICU from fetching instructions until the busy signa l is deasserted f or the first time. Th is is useful in situati ons where the processor block is reset by a core reset, bu ...

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    60 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R fastest rate at which a BIU can transfer instructions to the ICU (there is no limit to the number of cycles between two transfers). x All line transf ers assume the target instruction ( wo rd) ...

  • Xilinx UG018 - page 61

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 61 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R ISPLB Non-Pipe l ined Cacheable Se quential Fetch (Case 1) The t iming di agram in Figure 2-6 shows two consecu tive eight-word line fetch es tha t are not addres s pipelined. The example assumes instructions are fetched seq ...

  • Xilinx UG018 - page 62

    62 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R ISPLB Non-Pipe l ined Cacheable Se quential Fetch (Case 2) The t iming di agram in Figure 2-7 shows two consecu tive eight-word line fetch es tha t are not addres s pipelined. The example assum ...

  • Xilinx UG018 - page 63

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 63 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R The first line r ead (rl1) is requested by th e ICU in cycle 3 in r esponse to a cache miss (repr ese nted by the miss1 transaction in cycles 1 and 2). Instr uctions ar e sent fr om the BI U to the ICU fil l buffer in cycles ...

  • Xilinx UG018 - page 64

    64 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R After the first miss is detected, the ICU perfor ms a pr efetch in anticipation of requiring instructions from the next cache l ine (r epresented by the prefe t ch2 transaction in cycles 3 and ...

  • Xilinx UG018 - page 65

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 65 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R in cycles 10 through 15). The line is not cacheable, so instructions are not transferr ed fr o m the fill buffer to the instruction cac h e. ISPLB Pipelined Non-Ca cheable Sequential Fetch The t i mi ng d i ag r a m i n Fi g ...

  • Xilinx UG018 - page 66

    66 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R ISPLB 2:1 Core-t o-PLB Line Fetch The t iming di agram in Figure 2-12 shows an eight-wor d lin e fetch in a system with a PLB clock that runs at one half the frequency of the PowerPC 405 clock. ...

  • Xilinx UG018 - page 67

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 67 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R ISPLB 3:1 Core-t o-PLB Line Fetch The t iming di agram in Figure 2-13 shows an eight-wor d lin e fetch in a system with a PLB clock that runs at one thir d the frequency of the PowerPC 405 clock. The line read (rl1) is reque ...

  • Xilinx UG018 - page 68

    68 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Dat a-Side Processor Loc al Bus Interface The data-side pr ocessor local bus (DSPLB) interface en ables the PowerPC 405 da ta cache unit (DCU) to load (r ead) and stor e (write) dat a from an y ...

  • Xilinx UG018 - page 69

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 69 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R x The target addr ess of the da ta to be a ccessed is specified by the a ddress bus, C405PLBDCUABUS [0:31]. See “C40 5P LBD CUAB US[ 0:31] (Out put) ” . x The transfer size is spe ci fied as a single word or as eight wor ...

  • Xilinx UG018 - page 70

    70 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R i An eight-word line transfer moves t he eight-word ca ch e line aligned on the addres s specified by C405PLBDCUABUS[0:26 ]. See “C405PLBDCUABUS [0:31] (Output)” . This cache line contains ...

  • Xilinx UG018 - page 71

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 71 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R An eight-word line-write transfer occurs when the fill buffer r epl aces a n existing data- cache line containing modified data. The existing cache line is written to m emory before it is re p laced with the fill-buf fer con ...

  • Xilinx UG018 - page 72

    72 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Figure 2-15 : Data-Side PLB In terface Bloc k Symbol UG018_05_102001 PPC405 PLBC405DCUADDRACK PLBC405DCUSSIZE1 PLBC405DCURDDACK PLBC405DCURDDBUS[0:63] PLBC405DCURDWDADDR[1:3] PLBC405DCUWRDACK P ...

  • Xilinx UG018 - page 73

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 73 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Data -Side PLB Interface I/O Sig nal De script ions The following sections describe the operation of the data-s i de PLB interface I/O signals. Throughout these des criptions and un less otherwi se noted, the term clock refe ...

  • Xilinx UG018 - page 74

    74 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R If the transfer s ize is a si n gl e word, C405PLBDCUBE[0: 7] is also valid when the req u est is asserted. These si g nals specify which bytes ar e transferred be t ween the DCU and P LB slave ...

  • Xilinx UG018 - page 75

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 75 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R An eight-word line t ransfer moves the ca ch e line a ligned on the add ress speci fied by C405PLBDCUABUS[0:2 6]. This cache line contai ns the target data accessed by the DCU. The cache line is transferr ed using four doubl ...

  • Xilinx UG018 - page 76

    76 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R C405PLBDCUU0A TTR (Output) This signal r eflects the value of the user-defined (U0) stora g e attribute for the tar get addres s. The accessed data is no t i n a memory location charac teriz e ...

  • Xilinx UG018 - page 77

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 77 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Ta b l e 2 - 1 3 shows the possible values that can be pres ented by the byte enables and how they are interpr eted by th e PLB slave. All encoding of th e byte ena bles not shown are invalid and are not generated by the DCU ...

  • Xilinx UG018 - page 78

    78 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R C405PLBDCUPRIORITY[0:1] (Output) These signals are u sed to specify the priority of the data- access request. Ta b l e 2 - 1 4 shows the encoding of the 2-bit PLB-request priority signal. The p ...

  • Xilinx UG018 - page 79

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 79 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R an aborted data-write request. In this case, memory must no t be updated by the PLB slave and no further write acknowledgements can be pr esented by the PLB slave for the aborted req u e st . The DCU only aborts a data-acces ...

  • Xilinx UG018 - page 80

    80 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R PLBC405DCUADDRACK (Input) When as serted, this s ignal indica tes the P LB slave ac knowledges th e DCU data-access request (indicated by the DCU assertion of C405PLBD CUREQUEST). When deassert ...

  • Xilinx UG018 - page 81

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 81 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R must abort a DCU request (move no data) if the DCU assert s C405PLBDCUABORT in the same cycle the PLB slave acknowledges the r equest. The DCU supports up to thr ee outstanding requests over th e PLB (two read and one write) ...

  • Xilinx UG018 - page 82

    82 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R x During a sing le word write, the DCU replicates the data on the high and lo w words of the write data bus. The byte ena bles indicate which bytes o n the high word or low wor d are valid and ...

  • Xilinx UG018 - page 83

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 83 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R PLBC405DCURDWDA DDR[1:3] (Input) These signals are u sed to specify the transfer or der . They identify wh ich word or doubleword of a n eigh t-word line transfer is present on the DCU r ead-data bus when the PLB slave r etu ...

  • Xilinx UG018 - page 84

    84 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R is transferred fr om the DCU to the PLB slave. If this signal is deass erted, va lid data o n the write data bus has not been latched by the PLB slave. W rite-data acknowledgement is asserted f ...

  • Xilinx UG018 - page 85

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 85 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R The PLB sla ve should latch error information in D CRs so tha t software diagnost ic routines can attempt to repo rt and recover fr om the error . A bus-error address r egis ter (BEAR) should be im plemented for sto ring the ...

  • Xilinx UG018 - page 86

    86 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R x The DCU act ivity is s hown only a s an aid e in describing the examples. The occurrence and duration of this acti vity is not observable on the DS PLB. The following abbreviations appea r in ...

  • Xilinx UG018 - page 87

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 87 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R The second line read (rl2) is requested by the DCU in cycle 4. Th e BIU responds to this request after it has comple ted all transactions ass ociated with the first request (rl1) . Data is sent fro m the BIU to the DCU fill ...

  • Xilinx UG018 - page 88

    88 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R is sent fro m the BIU to the DCU fill buffer in cycle 7. The DCU uses the byte enables to select the appropriate bytes fr o m the read-data bus. The data is not cacheable, so the fill buffer is ...

  • Xilinx UG018 - page 89

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 89 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R The second wor d read (rw2) is r equested by the DCU in cycle 7 and the BIU responds in the same cycle. A single wor d is sent from the BIU to the DCU in cy cle 8. The DCU uses the byte enables to select the appro p riate by ...

  • Xilinx UG018 - page 90

    90 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R The third line write (wl3) cannot be star ted until the second request (wl2) is compl ete. This request is made by the DCU in cycle 13 in resp onse to the flus h3 request. The BIU r espon ds in ...

  • Xilinx UG018 - page 91

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 91 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R DSPLB Three Consecut i ve W ord Write s The t iming di agram in Figure 2-22 shows three consecutive wor d writes. It provides an example of the fastes t speed at which the DCU can r equest and send si ngle words over the PLB ...

  • Xilinx UG018 - page 92

    92 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R DSPLB Line W rite/Line Read/W ord Write The t iming di agram in Figure 2-23 shows a sequen ce involving an eigh t- word line write, an eigh t-word lin e read, and a w ord wri t e. It p rovides ...

  • Xilinx UG018 - page 93

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 93 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R DSPLB W ord Write/W ord Read/Wor d Write/Line Read The timing diagram i n Figure 2-24 shows a sequence in volving a word write, a word read, another wo rd write, and an eight-wo rd line read. The first word write (ww1) is r ...

  • Xilinx UG018 - page 94

    94 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R DSPLB W ord Write/Lin e Read/Line Write The t iming di agram in Figure 2-25 shows a sequen ce involving a word write, an eigh t- word line r ead, and an eight-word line write. It demonstrates h ...

  • Xilinx UG018 - page 95

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 95 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R DSPLB 2:1 Core-to- PLB Line Read The timing diagram in Figure 2-26 show s a line read in a syst em with a PLB clock that runs at one half the fr equency of the PowerPC 405 clock. The line read (rl1) is requested by the DCU i ...

  • Xilinx UG018 - page 96

    96 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R DSPLB 3:1 Core-to- PLB Line Write The t iming di agram in Figure 2-27 shows a line write in a syst em with a PL B clock that runs at one thir d the frequency of the PowerPC 405 clock. The line ...

  • Xilinx UG018 - page 97

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 97 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R DSPLB Abort ed Data-Access Request The t iming di agram in Figure 2-28 shows an aborted da ta-access request. The r equest is aborted because of a cor e reset. The BIU is not r ese t. A line write (wl1) is r equested by the ...

  • Xilinx UG018 - page 98

    98 www .xilinx.com PowerPC™ 405 Processor B lo ck R e fe ren ce Guid e 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Device-Control Register Interfaces The device-control register (DCR) int erface provides a mechanism for the processor block to initialize and control peripheral devices that reside on the same ...

  • Xilinx UG018 - page 99

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 99 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Internal Device Contro l Register (DCR) Interface The PowerPC 405 Pr ocessor block contains severa l internal device- control registers, which can be used to contro l, conf igure, and hold status for various functional units ...

  • Xilinx UG018 - page 100

    100 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R In V irtex-II Pro/Pr oX, a DCR access addressing the internal DCR logic could be visibl e on the external DCR bus interface as an access. V irtex-4-FX In V i rtex-4-FX pr o cessor blo cks, ther e ...

  • Xilinx UG018 - page 101

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 101 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R blocks that are associated with each PowerPC. Thus , this interface is not available to th e user for connection to the FPGA fabric. Figure 2-29 show s the block sy mbol for the dedicated EMAC DCR interface. For more i nfor ...

  • Xilinx UG018 - page 102

    102 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R In V irtex-II Pr o/ProX the PowerPC external DC R interface is clocked by the pr ocessor core clock (CPMC405CLOCK) , but in V irtex-4-FX th e external interface is clocked by an input to the proce ...

  • Xilinx UG018 - page 103

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 103 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R (CPMC405CLOCK), the access ti mes out. No err or is flagged on time-out. The processor just continues to execute the next instruction. Figure 2-31 illustrat es a logical implem entation of th e DCR bus interfa c e. This imp ...

  • Xilinx UG018 - page 104

    104 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Virt ex-4-FX The external general pu rpose DC R interface in V irtex-4-FX is identica l to it s predecessors with the follow ing exceptions: x Dedicated, r e-synchron i zation r egist ers implemen ...

  • Xilinx UG018 - page 105

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 105 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R External DCR Bus Interface I/O Signal Descriptions The followin g sections desc ribe the operation of the DC R interface I/O signals. Signa ls are presented with both V irtex-II Pro and V irtex-4-FX names. C405DCRREAD/EX TD ...

  • Xilinx UG018 - page 106

    106 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R The processor does not begin drivin g a ne w DCR address until th e DCR acknowled ge signal correspondin g to the previous DCR access has been d easserted for at le ast one cycle. C405DCRDBUSOUT[0 ...

  • Xilinx UG018 - page 107

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 107 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R DCR Interface 1:1 Clocking, Latched Acknowledge The example in Figure 2-33 assum e s th e follow ing: x The PowerP C 405 and the periphera l containing t he DCR are cl ocked at the sa me fr equency . x The acknowl e dg e si ...

  • Xilinx UG018 - page 108

    108 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R DCR Interface 2:1 Clocking, Latched Acknowledge The example in Figure 2-35 assum e s th e follow ing: x The PowerPC 405 D CR interface is clocked at twice the frequency of the peripheral containin ...

  • Xilinx UG018 - page 109

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 109 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R DCR Interface 1:2 Clocking, Latched Acknowledge The example in Figure 2-36 assum e s th e follow ing: x The PowerPC 405 DCR interface is clocked at half the fr equency of the peripheral containing the addr essed DCR. x The ...

  • Xilinx UG018 - page 110

    11 0 www .xilinx.com PowerPC™ 405 Processor Block Re fe ren ce Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R interrupts ahead of noncriti cal interrupts wh en they occur simult aneously ( c ert ain d e bug exceptions are handled at a lower priority). Cr itica l interrupts use a different save/restore re ...

  • Xilinx UG018 - page 111

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 111 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R EIC Interf ace I/O Signal Descriptio ns The following sections describe the operation of the EIC interface I/O signals. EICC405CRITINPUTIRQ (Input) When asserted, this signal indicates t he EIC is requesting that th e proce ...

  • Xilinx UG018 - page 112

    11 2 www .xilinx.com PowerPC™ 405 Processor Block Re fe ren ce Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R JT AG Interface I/O Signal Descriptions The following sections describe the operation of the JT AG interface I/O signals. JTGC405TCK (Input) This input is the JT AG TCK (T est ClocK) sig nal. The ...

  • Xilinx UG018 - page 113

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 11 3 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R C405JTGSHIFTDR (Output) This output is asserted (logic High) when the PPC405 T AP is in the Shift-DR state. Most designs do n ot require this signal an d should leave it un connected. C405JTGUPDA TED R (Output) T h i s o u ...

  • Xilinx UG018 - page 114

    11 4 www .xilinx.com PowerPC™ 405 Processor Block Re fe ren ce Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R The six least sign ificant bits of the pa rts Instruction Regi ster al ways compris e the FPGA Instruction Register . The remaining bits are ignored u nless the PPC405 cores a re connected in ser ...

  • Xilinx UG018 - page 115

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 11 5 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R The PPC405 cor es do not have their own BSDL files; instead, the necessary INSTRUCTION_OP CODES and other info rmation are incorporated in the device BSDL file. The PPC405 cor es are not available for in terconnect tests ( ...

  • Xilinx UG018 - page 116

    11 6 www .xilinx.com PowerPC™ 405 Processor Block Re fe ren ce Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Figure 2- 42: Corr ect Wiring of JT AG Chain s with Indiv idual PPC405 Connections ( Sep a rate JT AG Chains) PPC405 Core PPC405 Core JTGC405TDI C405JTGTDO JTGC405TMS JTGC405TCK C405JTGTDOEN JTGC ...

  • Xilinx UG018 - page 117

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 11 7 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Figure 2- 43: Correct Wiring of JT AG Chains with Individual P PC405 JT AG Connections (Internally Chai ned PPC405 Cores ) PPC405 Core PPC405 Core JTGC405TDI C405JTGTDO JTGC405TMS JTGC405TCK C405JTGTDOEN JTGC405TRSTNEG JTG ...

  • Xilinx UG018 - page 118

    11 8 www .xilinx.com PowerPC™ 405 Processor Block Re fe ren ce Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Figure 2 -44: Correct Wirin g of JT AG C hain with Multiplexed PPC405 Connection PPC405 Core JTGC405TDI C405JTGTDO JTGC405TMS JTGC405TCK C405JTGTDOEN JTGC405TRSTNEG PPC405 Core SEL JTGC405TDI C40 ...

  • Xilinx UG018 - page 119

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 11 9 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Connecting PPC405 JT AG L ogic in Series with the Dedicated Devi ce JT AG Logic An alternative to connectin g the PPC405 JT AG logic directly to pr ogra mm able I/O is to wire it in series wi t h the dedicated device JT AG ...

  • Xilinx UG018 - page 120

    120 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R When the PPC4 05 JT A G logic is con nected in se ries with the dedicated device JT AG logic, only one JT A G chain is required on the printed circuit board. All JT AG logic is accessed through th ...

  • Xilinx UG018 - page 121

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 121 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R For devices with more than one PPC405 core, users must connect the JT AG logic for ALL of the PPC405 cor es on the device when using th is connecti on style, even if some are not otherwise used. The JT AG signals are the on ...

  • Xilinx UG018 - page 122

    122 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R ); end component begin -- Component Instantiation U_PPC1 : PPC405 port map ( ... JTGC405TCK => TCK_IN, JTGC405TDI => TDI_IN, JTGC405TMS => TMS_IN, JTGC405TRSTNEG => TRSTNEG_IN, C405JTG ...

  • Xilinx UG018 - page 123

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 123 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R .C405JTGSHIFTDR (), .C405JTGUPDATEDR (), .C405JTGPGMOUT (), ... ); endmodule; -- Module: SINGLE_PPC_JTAG_SERIAL -- Description: VHDL instantiation template for serial connection of a -- single PPC405 core to dedicated JTA G ...

  • Xilinx UG018 - page 124

    124 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R signal TDO_PPC : std_logic; signal TMS_PPC : std_logic; signal TDI_PPC : std_logic; signal TCK_PPC : std_logic; begin -- Component Instantiation U_PPC1 : PPC405 port map ( ... JTGC405TCK => TCK ...

  • Xilinx UG018 - page 125

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 125 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R .C405JTGTDO (TDO_PPC), .JTGC405BNDSCANTDO (), .C405JTGTDOEN (TDO_TS_PPC), .C405JTGEXTEST (), .C405JTGCAPTUREDR (), .C405JTGSHIFTDR (), .C405JTGUPDATEDR (), .C405JTGPGMOUT (), ... ); JTAGPPC U_JTAG( TDOTSPPC (TDO_TS_PPC), TD ...

  • Xilinx UG018 - page 126

    126 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R component JTAGPPC port( TDOTSPPC : in std_logic; TDOPPC : in std_logic; TMS : out std_logic; TDIPPC : out std_logic; TCK : out std_logic; ); end component; signal TDO_TS_PPC : std_logic; signal TM ...

  • Xilinx UG018 - page 127

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 127 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R U_JTAG : JTAGPPC port map ( TDOTSPPC => TDO_TS_PPC, TDOPPC => TDO_OUT2, TMS => TMS_PPC, TDIPPC => TDI_PPC, TCK => TCK_PPC ); end TWO_PPC_JTAG_SERIAL_arch; // Module: TWO_PPC_JTAG_SERIAL // Description: Verilo ...

  • Xilinx UG018 - page 128

    128 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R .JTGC405BNDSCANTDO (), .C405JTGTDOEN (TDO_TS_OUT2), .C405JTGEXTEST (), .C405JTGCAPTUREDR (), .C405JTGSHIFTDR (), .C405JTGUPDATEDR (), .C405JTGPGMOUT (), ... ); JTAGPPC U_JTAG( TDOTSPPC (TDO_TS_PPC ...

  • Xilinx UG018 - page 129

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 129 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R Debug Int erface I/O Si gnal Descriptions The following sections describe the operation of the debug interface I/O signals. DBGC405EXTBUSHOLDACK ( Input) When asse rted, this signa l indicate s that the bus controller (f or ...

  • Xilinx UG018 - page 130

    130 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R In systems that deactivate the clocks to manage power , the debug halt signal should be used to restart th e clocks (if stopped) to enable an external debugger to operate the processor . After the ...

  • Xilinx UG018 - page 131

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 131 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R C405DBGST OP ACK (Output) When asserted, this signal indicates th at the PowerPC 405 is in d ebu g ha lt mode. When deasserted, the processor is no t in debug halt mo de. C405DBGLOADDA T AONAPUDBUS (Output, Virtex-4-FX only ...

  • Xilinx UG018 - page 132

    132 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R T race Inte rface I/O Signal Descriptions The following sections describe the operation of the trace i nterface I/O signals. C405TRCTRIGGEREVENTOUT (Output) When asserted, this signal indicates th ...

  • Xilinx UG018 - page 133

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 133 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R FPGA logic can combine these signals wi th the trigger-event output signal to produce a qualif ied version of the trig ger signal. The qua lified signal is wrapped to the t rigger-event input signal i n the same trace cycle ...

  • Xilinx UG018 - page 134

    134 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R C405TRCTRACEST A T US[0:3] (Output) These signal s provide additional in formation requ ir ed by a tra ce tool when reconstructin g an instruction execution sequence. This information is collected ...

  • Xilinx UG018 - page 135

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 135 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R PVR Interface I/ O Signal Descriptions The following sections describe the operation of the PVR-interface I/O signals. TIEPVRBIT8 (Input) When tied hig h sets Processor V ersi on Register bit 8 to 1. TIEPVRBIT9 (Input) When ...

  • Xilinx UG018 - page 136

    136 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R Additional F PGA Specific Signals Figure shows the block symbol for the additional FPGA signals used by the processor block. The sig nals are summarized in Ta b l e 2 - 3 0 . Additi onal FPGA I/ O ...

  • Xilinx UG018 - page 137

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 137 UG018 (v 2. 0) Aug ust 20, 2004 1-800- 255 -7778 R MCBTIMEREN (Input) When asserted, this signal indicates that the enable for the timer clock zone (CPMC405T IM ERCLKEN) should follo w (match the value of) the glo bal write enable (GWE) during the FPGA startup sequence. Whe ...

  • Xilinx UG018 - page 138

    138 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 UG018 ( v2.0) Au gust 20, 2004 Chapter 2: Input/Output Interfaces R ...

  • Xilinx UG018 - page 139

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 139 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Chapter 3 PowerPC 405 OCM Contr oller Intr oducti on The On-Chip Memo ry (OCM) controller serves as a dedicated in terface between the FPGA BRAMs and the OCM signals contained w ithin the embedded PPC405 core. The OCM con ...

  • Xilinx UG018 - page 140

    140 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Comp arison of V irtex-II Pro an d Vir t ex-4 OCM Controllers The V irtex-4 OCM controller is com pletely backward compatible with the Virtex- I I Pr o OCM controller . Ta b l e 3 - 1 hi gh ...

  • Xilinx UG018 - page 141

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 141 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Features for Instru ction-Side OCM (ISOCM) The ISOCM interface con tains a 64 - b it read on ly po rt for instruction fetches and a 32-bit read and write port to initialize or test the ISBRAM. x 64-bit Data Rea d Only bus ...

  • Xilinx UG018 - page 142

    142 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R OCM Controll er Operation The OCM contro ll er is distributed into two blocks, one fo r th e ISOCM interface and the other for the DSOCM interface, as shown in Figure 3-1 . The DSOCM and IS ...

  • Xilinx UG018 - page 143

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 143 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R up with t h e value on the in put ports: DSARCV ALUE[0:7] and ISARCV ALUE[0:7] respectively . The two registers can a lso be load ed us ing DCR write a ssembly instructions (mtdcr) . The value of DSARC and ISARC defines t ...

  • Xilinx UG018 - page 144

    144 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R register d efin e s the 16 MB memory region that is valid fo r the DSOCM. Loa d in structions have a priority over store i nstructions at the DSOCM interface Non-Memory Peripher als for DSO ...

  • Xilinx UG018 - page 145

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 145 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R DSOCM Port s Figure 3-2 and Figure 3-3 ar e the block diagrams of the DSOCM in V irtex-4 and V irtex-II Pro. All signals are in big endian format. Figu re 3-2: DSOCM Int erface for Virtex-4 UG018_37b_12080 3 RESET DSOCMBR ...

  • Xilinx UG018 - page 146

    146 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R DSOCM Input Ports Ta b l e 3 - 3 describes the Da t a Side OCM (D SOCM) input ports. T able 3-3: DSOC M Inp ut Port s Port Direct ion Descript ion BRAMDSOCMCLK Input Thi s signal clocks the ...

  • Xilinx UG018 - page 147

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 147 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R DSOCM Input Ports: Attributes Attributes are inputs to th e OCM controller from the FP GA fabric that must be connected to initialize registers at FPG A power up, or following a processor reset. These inputs a re used to: ...

  • Xilinx UG018 - page 148

    148 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R DSOCM Output Ports Ta b l e 3 - 5 describes the data-side OCM (DSOCM) outpu t ports. T able 3-5: DSOCM Output P orts Port Direct ion Descript ion DSOCMB RAMEN O utput This is the BRAM enabl ...

  • Xilinx UG018 - page 149

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 149 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R DSOCM-to-BRAM Interfaces Figure 3-4 provides an example of a basic DSOCM-to-BRAM interface fo r V irtex-II Pro. V irtex-II P ro supports on ly fixed laten cy connec tions such as the on e shown. Figure 3-5 shows an exampl ...

  • Xilinx UG018 - page 150

    150 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Figu re 3-4: DSOCM to BRAM Interfac e: 8-KBy te Example for Virtex-II Pro UG018_48_112103 DSOCMBRAMABUS[19:29] DSOCMBRAMWRDBUS[0:31] DSOCMBRAMBYTEWRITE[0:3] BRAMDSOCMCLK DSOCMBRAMEN BRAMDSO ...

  • Xilinx UG018 - page 151

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 151 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Note: For back war d co mp atibility with V irtex-II Pro, w he n conn ecting DSOC M to BRAM (as show n in Figure 3-5 ), set DSOCM RWCOMPLETE t o logic 1 an d leave the DSOC MRDADDR V ALID an d DSOC MWRADDR V ALID signals ...

  • Xilinx UG018 - page 152

    152 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Figure 3-6 shows the extended feature in V irtex-4 for DSOCM-to-Memory-Mapped-Slave- Peripheral interface. ISOCM Ports Figure 3-7 and Figure 3-8 ar e block diagrams of the ISOCM in V irtex- ...

  • Xilinx UG018 - page 153

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 153 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R ISOCM Input Ports Ta b l e 3 - 6 describes the Instruction Side OCM (ISOCM) input ports. Figure 3- 8: ISOCM Interfac e for Virtex- 4 ISOCMDCRBRAMEVENEN (Virtex-4 Only) ISOCMDCRBRAMODDEN (Virtex-4 Only) UG018_38b_11210 3 R ...

  • Xilinx UG018 - page 154

    154 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R ISOCM Input Port s, Attributes Attributes are inputs to th e OCM controller , from the FPGA fabric, that must be conn ected to initialize co ntrol re g isters at FPGA powe r-up, or followin ...

  • Xilinx UG018 - page 155

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 155 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R ISOCM Output Ports Ta b l e 3 - 8 describes th e instruction-sid e OC M (ISOCM) output ports . T able 3-8: ISOCM Output P orts Port Direct ion Descript ion ISOCM BRAMEN Output Th is is a BRAM read enable from the ISOCM co ...

  • Xilinx UG018 - page 156

    156 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R ISOCMBRAMEVENW RITEEN Output Note: Option al. Used in du al-port BRAM inte rface design s only . W ri te enable to qual ify a valid wri t e into a block RAM via a DCR- based access. This si ...

  • Xilinx UG018 - page 157

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 157 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Figure 3-9 shows an example of an ISOCM-to-BR A M in terface in V irtex-II Pro. Figure 3-10 shows an example of an ISOCM-to-BRAM i nterface in V irtex-4. Figure 3 -9: ISO CM to BRAM Int erface: 8 KByt e Example in Virtex- ...

  • Xilinx UG018 - page 158

    158 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Note: See Ta b l e 3 - 8 for descriptions of the sign als shown in Ta b l e 3 - 1 0 , above. Progra mmer’ s Model DCR Registers Application so ftware has read and write access to the DCR ...

  • Xilinx UG018 - page 159

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 159 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R locations. These bits are decod ed agains t PPC405 address bits 0:7. These eight most significant address bits permit the OCM controllers to reside independ ently in any 16 MB, non-cacheable, memory range w i thin the PPC ...

  • Xilinx UG018 - page 160

    160 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R ISCNTL Registers Ta b l e 3 - 1 1 an d Ta b l e 3 - 1 2 describe the ISCNTL registers in V irtex-II Pro and V irtex-4 devices. For additiona l in formation, refer to Figure 3- 13 , page 164 ...

  • Xilinx UG018 - page 161

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 161 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Features Int roduced in V irtex-4 and Comparison with Virte x -II Pro In V irtex-4 an optional aut o clo c k rati o detectio n feature was implemented on both the DSOCM and ISOCM . If bit 3 (Enable Auto Clo ck Ratio Detec ...

  • Xilinx UG018 - page 162

    162 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Figure 3-1 1: DSOCM DC R Registers for Virtex-II Pro UG018_46_042304 DSARC (DSOCM Address Range Compare Register) User Programmable Registers Allocated within DCR address space (Programmer& ...

  • Xilinx UG018 - page 163

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 163 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Figure 3-12 : DSOCM DC R Registers for Virtex-4 UG018_46b_042304 DSARC (DSOCM Address Range Compare Register) User Programmable Registers Allocated within DCR address space (Programmer's Model) 8 bits: Address range ...

  • Xilinx UG018 - page 164

    164 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Figure 3- 13: ISOCM DCR Registers for Virtex-II Pro UG018_47_04230 4 ISARC (ISOCM Address Range Compare Register) User Programmable Registers Allocated within DCR address space (Programmer& ...

  • Xilinx UG018 - page 165

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 165 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R The following section describes th e DCR bit mapping durin g r ea d/write operation s on the ISINIT and ISFILL registers. Figure 3- 14: ISOCM DCR Registers for Virtex-4 UG018_47b_05120 4 ISARC (ISOCM Address Range Compare ...

  • Xilinx UG018 - page 166

    166 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R DCR Wri te Access As shown in Figur e 3 -15 , ISINIT is a 22-bit register (A8-A29) that is mapped to DCR write data bus bits D8-D29. The write address on the memory inter face is A8-A28, an ...

  • Xilinx UG018 - page 167

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 167 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R DCR Read Access If the ISINIT r egi ster is read back on the DCR: x For V irtex-II Pro, bits A8-A29 are mapped onto DCR read data bus bits D0-D21 as shown in Figure 3-1 6 , please n o te that the mapping for read access i ...

  • Xilinx UG018 - page 168

    168 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Figure 3 -16: ISOCM: I SINIT and IS FILL Desc riptions (Rea d Access) for Virtex II- Pro UG018_69_042304 R ead Data on DCRDBUS C ontent in ISINIT Register ISINIT (ISOCM Initialization Addre ...

  • Xilinx UG018 - page 169

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 169 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R BRAMs that interface with the ISOCM co nt roller can also be initialized thr ough the configuratio n bit-stream, during FPG A configurat ion. The Data 2MEM softw are utility in the design flow tools can be used to load IS ...

  • Xilinx UG018 - page 170

    170 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R routing delays, signal lo ading, BRAM mem ory access time, clock to ou tput times, and setup and hold times of the BRAM an d processor blocks. Users may need to go through multiple iteratio ...

  • Xilinx UG018 - page 171

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 171 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R In multi-cycle mo de, initial wait cycles are inserted until the CPMC 4 05CLOCK and BRAMISOCMCLK ris ing edges are aligned. After the initial startup la tency , two instructions (64 bits) can be fetched every two BRAM clo ...

  • Xilinx UG018 - page 172

    172 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R In order to estimate the theoretical maximu m number of instruction fetches per second on the OCM interface, measur e the period of the BRAM clock cycle to determine the maxi mum thr oughpu ...

  • Xilinx UG018 - page 173

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 173 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R mode and multi-cycle Mode. The timing interface betwee n the O CM controller and the memory is always w ith respect to the BRAMISOCMCLK. Figure 3-20 : Sin gle Cycle Mo de (1:1) ISO CM Write Timing UG018_66_03060 3 C PMC40 ...

  • Xilinx UG018 - page 174

    174 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R DSOCM Data Load, Fixed Lat ency Figure 3-22 and Figure 3-23 s how two back- to-back loads f or single-cycle m ode and mu lti- cycle mode with a CPMC405 CLO CK:BRAMDSOCMCLK ratio of 2:1. Not ...

  • Xilinx UG018 - page 175

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 175 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R In multi-cycle mo de, initial wait cycles are inserted until the CPMC 4 05CLOCK and BRAMDSO CMCLK rising edges are aligned . After the ini tial startu p latency , one load (32 bits) can be completed eve ry two BRAMDSOCMCL ...

  • Xilinx UG018 - page 176

    176 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R In the figur es above, L_addr_ n refers to the OCM controller addr ess o utputs DSOC MBRA MR DAD DR and Rd_d ata_ n refers to the OCM contr oller data bus inputs BRAMDSOCM RD DBUS fr om the ...

  • Xilinx UG018 - page 177

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 177 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R period should be used. Note that th is is only an estimate of store performance on the interface. In the figur es above, S_addr_n r efers to the OCM controller a ddress outputs DSOC MBRA MW RAD DR and St_dat a_n refe rs t ...

  • Xilinx UG018 - page 178

    178 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R DSOCM Data Load, V ariable Latency Figure 3-26 and Figure 3-27 show two loa d operat ions with va riable latency for singl e cycle mode and multi-cycle mode with a CP MC405CLOCK:BRAMDSOCMCL ...

  • Xilinx UG018 - page 179

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 179 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R DSOCM Data S tore, V ariable Latency Figure 3-28 and Figure 3-29 show two store operations with va ria ble latency for singl e- cycle mode and for multi-cycle mode wi th a CPMC405CLOCK:BRAMDSOCMCLK ratio of 2:1 . In both ...

  • Xilinx UG018 - page 180

    180 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R Figure 3-28 : Sin gle Cycle Mo de (1:1) DS OCM Write V ariable Latency Virtex-4 UG018_64c_12080 3 C PMC405Clock D SOCM 1:1 Data Store Timing (Variable latency, DSOCMRDWRCOMPLETE driven by O ...

  • Xilinx UG018 - page 181

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 181 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Application Note s and Reference Desi gns Xilinx provides several appli cation notes and reference designs utiliz ing the OCM controllers. Design examples in clud e: x Booting the PP C405 from on-chip memory . x Using the ...

  • Xilinx UG018 - page 182

    182 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 3: Pow erPC 405 OCM Controlle r R ...

  • Xilinx UG018 - page 183

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 183 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Chapter 4 PowerPC 405 APU Contr oller This chapter only a pplies to the PowerPC 40 5 in the V irtex-4-FX fami ly and covers the following to pics: x “FC M Instruc tion Process ing” x “APU Co ntroller Conf iguration? ...

  • Xilinx UG018 - page 184

    184 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R The APU Contr o ller serves two purposes: It performs clock domain synchronization between the fast PowerPC clock and the slow FCM interface clock, a nd it can be configured to decode certa ...

  • Xilinx UG018 - page 185

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 185 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R has a config urable format an d is a true extension of the PowerPC in struction set arch i tecture (ISA). Enabling the APU Control ler The PowerPC MSR regist er must be con figure d befor e the processor can use the APU c ...

  • Xilinx UG018 - page 186

    186 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R Blocking Ins tr uctions Any non-autono mo us instruction that cann ot be predictably aborted and later re-issued must be blocking. During execut ion of a blocki ng ins truction, all in terr ...

  • Xilinx UG018 - page 187

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 187 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Instruct ion Decoding FCM instructions can be decod e d either by th e APU Co ntroller or by the FCM itself. APU Contr o ller decoding benefits fr om the higher clock frequencies possible i nside the hard core. This resul ...

  • Xilinx UG018 - page 188

    188 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R The decode d instructions require an FCM f loating po int unit to be us ed. FPU in structions that return results to the PowerPC will d e f ault to execute as non-a utonomous, no n- blockin ...

  • Xilinx UG018 - page 189

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 189 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R The extended op-code for Lo ad/Stor e operations are described in Ta b l e 4 - 3 . APU Controller Load/S tore ins truction decodi ng can be disabled in the APU Contr o ller configuration register . The PowerPC405 na tive ...

  • Xilinx UG018 - page 190

    190 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R FCM User-Defined Instruction Deco ding User -defined instructions that are not recogn ized (i.e., decoded) by the APU Contr oller are passed to the FCM for deco d ing in fabric logic. While ...

  • Xilinx UG018 - page 191

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 191 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R FCM inter nal data hazar ds such as r ead-after -write (RA W) and write-af ter-wri te (W A W) are eliminated if the desi gner ensures that a ll FCM ins tructions compl ete in order . This can be done conservatively by as ...

  • Xilinx UG018 - page 192

    192 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R UDI Configuration Registers The APU Controller includes eight U DI configuration registers. This allo ws the user to define as man y custom ins tructions and have th em decoded in the fast ...

  • Xilinx UG018 - page 193

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 193 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R The reset value of the individual UDI r egisters can be defined using a ttribute inputs to the APU Contr oller . For deta ils see the “APU Controller Attributes” section in this chapter . DCR Access to the Configurati ...

  • Xilinx UG018 - page 194

    194 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R APU Controller Input Signals All APU Con troller input sig nals shou ld be s ynch ronized on the FCM clock (CPMFCMCLK). T able 4-6: FCM Interface Input Signals Signal Function FCMAPU INS TR ...

  • Xilinx UG018 - page 195

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 195 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R FCMAP U DCDLDSTWD F CM decoded loa d/store instruction does w ord transfer . FCMAPUDCDLDSTDW F CM decoded load/stor e instruction do es double word tran sfer . FCMAP U DCDLDSTQW FCM deco ded load/store instructio n d oes ...

  • Xilinx UG018 - page 196

    196 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R APU Controller Outpu t Signa ls All APU Con troller output signals are synchronou s wit h the FCM clo c k ( CPMFCMCLK). T able 4-7: FCM Interface Output Signals Signal Fu nc tion APUFCM INS ...

  • Xilinx UG018 - page 197

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 197 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R APU Controller Attribut es The following input signal s are used as reset values for the APU Controller configurat ion registers. Th e reset values can be over -w ritten using DCR. For details see the “APU Controller Co ...

  • Xilinx UG018 - page 198

    198 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R T able 4-10: Bit Map Between TIEAP UCONTROL and APU Configuration Register APU Controller Configuration Field TIEAPUCONTROL Bits LdStDecDis 0 UDIDecDis 1 ForceUDINonB 2 FPUD ecDis 3 FPUCAri ...

  • Xilinx UG018 - page 199

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 199 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R FCM Interface Timing S p ecification Auton omous T ransact ions Note: Actual timing result s may var y from those shown in Figu re 4-3 . For exampl e, the instructio n and ope rands can be valid on the same FCM clock cycl ...

  • Xilinx UG018 - page 200

    200 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R Note: Actual timing result s may var y from those shown in Figu re 4-4 . For exampl e, the operand s could c ome later than sho wn. Figure 4- 4: FCM Decoded Autonomous T ransaction Ex a mpl ...

  • Xilinx UG018 - page 201

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 201 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Blocking T ransact ions Note: Actual timing result s may var y from those shown in Figu re 4-5 . For exampl e, the operand s could c ome later than sho wn. Figure 4- 5: FCM Decoded Blocking T ransaction Example UG018_04_0 ...

  • Xilinx UG018 - page 202

    202 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R Non-Blocki ng T ransactions Note: Actual timing result s may var y from those shown in Figu re 4-6 . For exampl e, the operand s could c ome later than sho wn. Figure 4-6: APU C ontroller D ...

  • Xilinx UG018 - page 203

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 203 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R FCM Load Instruction Note: Load dat a can arri ve at the s ame time as the instruc tion or at a later cloc k cycle t han shown in Figure 4-7 . Figure 4 -7: APU Controller Decoded Load Instruction Example UG018_04_06_04230 ...

  • Xilinx UG018 - page 204

    204 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R Note: Load dat a can arri ve at the s ame time as the instruc tion or at a later cloc k cycle t han shown in Figure 4-8 . Also, lo ad data m ight not be se nt back-to-back . Users shoul d l ...

  • Xilinx UG018 - page 205

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 205 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R FCM Exception Note: FCMAPUEXEPTION m ay be sent at a ny time d uring the execu tion of a non-auto nomous instr ucti on. Figure 4 -10: APU Controller Deco ded Store Instru ctio n with StoreWB OK=1 UG018_04_09_032504 CPMFCM ...

  • Xilinx UG018 - page 206

    206 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Chapter 4: P owerPC 405 AP U Controller R FCM Decoding Using Decode Busy Signal Figu re 4-12 : FCM Deco de Asserting DecodeBusy UG018_04_11_032504 CPMFCMCLK APUFCMINSTR UCTION APUFCMINSTR V ALID FCMAPUDECODEBUSY FCMAPU OPTIONS FCMA ...

  • Xilinx UG018 - page 207

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 207 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Appendix A RISCW atch and RISCT race Interfaces This appendix summarizes the interface r equirements between the PowerPC 405 and th e RISCW atch and RI SCT r ace tools . The r equirement for separate JT AG and trace conne ...

  • Xilinx UG018 - page 208

    208 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix A: RISC W atch a nd RISCT ra ce Interface s R T able A-1: JT AG Connector Signals for RISCWa tch Pin RISCW atch Descrip tion I/O Signal Name 1 I nput TDO J T AG test-da ta out. 2 No Co nnect Res erved 3O u t p u t T D I a ...

  • Xilinx UG018 - page 209

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 209 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R RISCT race Interface The RISCT race tool communicates with the PowerPC 405 using the trace i nterface. It requires a 20 -pin , mal e 2x10 he ade r connec tor (3M 35 92-6 002 or equiva lent ) locat ed on the targ et develo ...

  • Xilinx UG018 - page 210

    210 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix A: RISC W atch a nd RISCT ra ce Interface s R T able A-3: T race Connector Signals for RISCT race Pin RISCT race Description I/O Sig nal Name 1N o Con nect Reserved 2N o Con nect Reserved 3 O utput T rcClk T race cycle. 4 ...

  • Xilinx UG018 - page 211

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 21 1 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R T able A-4: PowerPC 405 to RISCT race Signal Mapping PowerP C 405 RISCT race T race Connector Pin Mictor Connector Pin Signal I/O Signal I/O C405TRCCYCLE Output T rcClk Input 3 6 C405TRCODDEXECUTIONST A TUS[0] Ou tput TS ...

  • Xilinx UG018 - page 212

    212 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix A: RISC W atch a nd RISCT ra ce Interface s R ...

  • Xilinx UG018 - page 213

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 213 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Appendix B Signal Summary Interface Signals Ta b l e B - 1 lists the PowerP C 405 interface signals in alphabetical order . A cross reference is provided to each signal d escription. Th e sign al naming conve nti ons u se ...

  • Xilinx UG018 - page 214

    214 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Appendi x B: Signal Summa ry R APUFCMXERCA V- 4 O F C M N o Connect Ref lects th e XerCA bit use d for extended a r ithmetic. BRAMDSOCMCLK V -II Pro and V -4 I DSOCM 1 Clocks the DS OCM contr oller and the data side interface l ogi ...

  • Xilinx UG018 - page 215

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 215 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R C405JTGCAP TU REDR (OUTPUT) V -II Pro and V -4 OJ T A G N o Connect Indicates the T AP controll er is in the capt ure- DR sta te. C405JTGEXTEST (OUTPUT) V -II Pro and V -4 OJ T A G N o Connect Indicates t he JT AG EXTEST ...

  • Xilinx UG018 - page 216

    216 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Appendi x B: Signal Summa ry R C405PL BICUABUS[0: 29] V -II Pr o and V -4 OI S P L B N o Connect Specifies the memory addr es s of the instruc tion-fetch re quest. Bits 30 :31 of the 32-b it addr ess are assu med to be zer o. C405P ...

  • Xilinx UG018 - page 217

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 217 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R CPMC 405TIMERCL KEN V -II Pro and V -4 I CPM 1 Enables the timer clock z one. CPMC 405TIMER TICK V -II Pro and V -4 I CPM 1 Inc rements o r decrem en ts th e PowerPC 405 timers ev ery time it is acti ve wit h th e CPM C 4 ...

  • Xilinx UG018 - page 218

    218 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Appendi x B: Signal Summa ry R EICC405EXTINPUTIRQ V -II Pro and V -4 I EIC 0 Indicate s an extern al noncrit ical inter rupt occurred. FCMAPUCR[0:3 ] V -4 I FCM 0 Condition r esult bits to set in the PowerPC CR field FCMAPUDCDCREN ...

  • Xilinx UG018 - page 219

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 219 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R FCMAPU DONE V -4 I FCM 0 Indicates the completion of the instruc t ion in the FCM to t he APU Con trol ler FCMAPUEXCEPTION V -4 I FCM 0 FCM generate progr am exception on the pr ocessor (vector 0x0700) . FCMAPUEXEBLOCKING ...

  • Xilinx UG018 - page 220

    220 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Appendi x B: Signal Summa ry R IS OCMDC RBR AMR DSE LECT V -4 O ISOCM No Connect S elect between e ven and odd instruction words fr om DCR access JTGC405BNDSCANTDO (INPUT) V -II Pro and V -4 I JT AG 0 JT AG b oundary scan input fro ...

  • Xilinx UG018 - page 221

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 221 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R PLBC40 5D CU WRDACK (INP UT) V -II Pro and V -4 I DSPLB 0 Indicates the da t a on t he DCU write- data bus is being ac c epted by the P LB slave. PLBC40 5I CUADDRAC K (INPUT) V -II Pro and V -4 I ISPLB 0 Indicates a PLB s ...

  • Xilinx UG018 - page 222

    222 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Appendi x B: Signal Summa ry R TIEC405DETERMIN ISTICMUL T (INPUT) V -II Pro and V -4 I Control 0 Required Specifi es whether all mult iply operations co mplete in a fixed number of cycles or have a n early -out capabili ty . TIEC40 ...

  • Xilinx UG018 - page 223

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 223 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Appendix C Pr ocessor Block T iming Model This section explains all of the timing parameters associated with the IBM PPC405 Processor Block. It is intended to be used in conjunction with Module 3 of the V irtex-I I Pr o o ...

  • Xilinx UG018 - page 224

    224 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix C: Proce ssor Block Timing Mo del R PowerPC misc el laneo u s (PPC ), T race Port (TRC), JT AG, Instruct i on-Si de On-Chip Memory (ISOCM), and Dat a-Side On-Chip Mem ory (DSOCM), Auxiliary Processor Unit Controller (APU, ...

  • Xilinx UG018 - page 225

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 225 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R T able C -2: P arameters Rel ative to th e Core C lock (CPMC4 05CLOCK) Parameter Function Signals Setup/Hold: T PCCK _DC R/T PCK C _DCR a Control Inputs DCRC405ACK T PDCK _DCR/T PCK D _DC R a Data Inpu ts DCRC405D BUSIN[0 ...

  • Xilinx UG018 - page 226

    226 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix C: Proce ssor Block Timing Mo del R Clock: T CPWH Clock Pulse W idth, High State CPMC405CLOCK T CPWL Clock Pulse W idth, Low State CPMC405CLOCK a. V irtex-II Pro only . See Ta b l e C - 3 for V irtex-4 DCR bus timing para ...

  • Xilinx UG018 - page 227

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 227 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R T able C -3: P arameters Rel ative to the DCR Bu s Clock (CPMDC RCLK, Virtex-4 Only ) Parameter Function Signals Setup/Hold: T PPCDCK _EXDCRACK T PPCCKD _EXDCRACK Control Inputs EXTDCRC405ACK T PPCDCK _EXDCRDBUS T PPCCKD ...

  • Xilinx UG018 - page 228

    228 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix C: Proce ssor Block Timing Mo del R T able C -4: P arameter s Relative to the FCM Clo ck (CPM FCMCLK, Virtex -4 Only) Parameter Function Signals Setup/Hold: T PCCK_ FCM/T PCKC _FC M Control Inputs FCMAPUINSTRACK FCMAPUDO ...

  • Xilinx UG018 - page 229

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 229 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R T PCKD O _FCM Data Outputs APUFCMINSTRUCTION [0:31] APUFCMRADA TA[0:31] APUFCMRBDATA [0:31] APUFCMLOAD DATA[0:31] Clock: T fcmpwh and T FCMPWL Clock High W idth Clock Low W idth CPMFCMCLK T able C -4: Parameters Relative ...

  • Xilinx UG018 - page 230

    230 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix C: Proce ssor Block Timing Mo del R T PCKD O _PLB Data outputs C405PL BDCUWRDBUS[0:6 3] T PCKA O _PLB Address outputs C405PLBDCUABUS[0 :31] C405PLBICUABUS[ 0:29] Clock: T PPWH Clock pulse width, High state PLBCLK T PPWL C ...

  • Xilinx UG018 - page 231

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 231 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R Clock to Out: T PCKCO _ISOCM Con tr ol ou tputs ISOCMBRAMEN ISOCMBR AMODDWRITEEN ISOCMBRAMEVEN WRITEEN ISOCMDCRBRAMEVENEN (V irtex-4 only) ISOCMDCRBRAM ODDEN (V irtex-4 on ly) ISOCMDCRBRAMRD SELE CT (V irtex-4 only) T PCK ...

  • Xilinx UG018 - page 232

    232 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 Append ix C: Proce ssor Block Timing Mo del R Figure C-2: Processor Block Timing Relative to Clock Edge CLOCK CONTROL INPUTS CONTROL OUTPUTS D ATA OUTPUTS D ATA INPUTS ADDRESS OUTPUTS T x PWH T PCCK T x PWL T PCKC T PCKCO T PCKDO T ...

  • Xilinx UG018 - page 233

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 233 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 A abort data-side PLB 78 , 97 instruction-side PLB 54 , 67 address ack nowledge data-side PLB 80 instruction-side PLB 55 address bus data-side PLB 74 DCR 10 5 instruction-side PLB 52 address pipelining cachea b le f e tch 6 ...

  • Xilinx UG018 - page 234

    234 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 R cachea ble 49 non-cacheable request size 48 prefetching 49 without all oc ate 49 FIT description of 29 timer exception 39 upda te f req uency 38 fixed-interval timer See FIT. G general-purpose register See GPR. global clock gatin ...

  • Xilinx UG018 - page 235

    PowerP C ™ 405 Process or B l oc k Referenc e G ui de www .xilinx.com 235 UG018 (v 2. 0) A ugu st 20, 200 4 1-800- 255 -7778 R processor reset See core reset. programmabl e- interval timer See PIT. R read ackn ow l e dge data-side PLB 82 instruction-side PLB 56 read not write 74 read request 68 address pipelining 71 cachea ble 70 DCR 10 5 unalig ...

  • Xilinx UG018 - page 236

    236 www .xilinx.com PowerP C™ 405 Proces sor Block Re ference Guide 1-800- 255-7778 U G018 (v 2.0) Au gust 2 0, 2004 R ...

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