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Intel 21555 - page 1
21555 PCI-to-PCI Bridge Evaluation Board User’s Guide November 20 02 Order Num ber: 27835 9-002 ...
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Intel 21555 - page 2
21555 PCI-to-P C I Br idge Evalua tion Board User’s G uide Informati on in this document is provide d in con nection w ith Intel® products. No license, express or implied, b y estop pel or oth erwise, to any intellectual property r ights is granted by this document. Excep t as provided in Intel's T erms and Conditions o f Sale for such p ro ...
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Intel 21555 - page 3
21555 PCI -to-PCI Bridge Ev aluation Board User ’ s Guid e iii Contents 1 Introducti on............ ................... ............. ................... .................... ................... ............. ...... 5 1.1 Overview .. ................... ............. ................... .................... ................... ............. ..... ...
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Intel 21555 - page 4
iv 21555 PCI-to-P C I Br idge Evalua tion Board User ’ s Guide Tables 1 DIP Swi tch Operat ion ..... .................... ................... ............. ................... ................ 9 2 Stake-P in Jumper .... ................... ............. ................... .................... ............. ......... 9 3 Clock Configurati on Jump ...
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Intel 21555 - page 5
21555 PCI -to-PCI Bridge Ev aluation Board User ’ s Guid e 5 Introduction 1 This User’ s Guide descri bes the 21555 PCI-to -PCI non transpar ent Bridge Evalu ation Board which is referred to as the DE1B55503. 1.1 Overview The DE1B55503 is a PCI exp ansion bo ard that is used to evaluate the o peration of the 21 555 when it is used as a gateway ...
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Intel 21555 - page 6
6 21555 PCI-to-P C I Br idge Evalua tion Board User ’ s Guide Introduction 1.3 Major Co mponent s Figure 1 on page 6 show s the maj or components on the DE1 B55503. 1.3.1 Connectors • J1 is the 10-pin J T AG conn ector . See T able A-5 on page 26 . • J7 and J1 01 (slot 2 and slo t 1) are local (secondar y bus) P CI option slots. — J101 (slo ...
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Intel 21555 - page 7
21555 PCI -to-PCI Bridge Ev aluation Board User ’ s Guid e 7 Introduction Note: See T able A-2 on page 24 for Micto r pinouts . 1.3.2 Switches and Jumper The DE1B5550 3 uses a combination of DIP switch, stake- pin and zero o hm resistor jumpers to control the various co nfiguration optio ns. See Section 1.4 , Section 1.5 , and Section 1.6 for inf ...
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Intel 21555 - page 8
8 21555 PCI-to-P C I Br idge Evalua tion Board User ’ s Guide Introduction 1.4 Switch Setti ngs Figur e 2 shows the three initialization switch packs, and T able 1 on page 9 gives a high-level description of each switch. The switches are r ead at DE1B55503 power up. Furthe r details on the operation o f these switches can be found in Chapter 3, ? ...
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Intel 21555 - page 9
21555 PCI -to-PCI Bridge Ev aluation Board User ’ s Guid e 9 Introduction 1.5 S t ake- Pi n Ju mp er Ta b l e 2 shows the con figuration and th e function of the single stake-pin jumper . J8 enables the DE1B55503 hot-swa p function ality , controls o peration of LED L1, and connects t he l_stat signal to a pullup resisto r . T able 1. DIP Switc h ...
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Intel 21555 - page 10
10 21555 PCI-to-P C I Br idge Evalua tion Board User ’ s Guide Introduction 1.6 Resistor Jum pers Figur e 3 shows the location of the zero (0) ohm resis tor config uratio n jumpers. They control the clock configu ration and the clamping v oltage. T o alter the factory configurati on of t he DE1B5550 3, the jump ers must be s oldered on o r of f t ...
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Intel 21555 - page 11
21555 PCI -to-PCI Bridge Ev aluation Board User ’ s Guid e 11 Introduction 1.6.1 Clock Configuration Ta b l e 3 describes the resistor jumpers to install that connect p_clk and s_clk_o to the Mictor connectors. T o improve sign al integrity and mini mize noise, these signals are not wired to the Mictor connectors. Resi stor jumpers also con trol ...
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Intel 21555 - page 12
12 21555 PCI-to-P C I Br idge Evalua tion Board User ’ s Guide Introduction 1.7 Secondary Slot Num bering and IDSEL Mapp ing Figur e 4 gives the bus s lot numberin g. Ta b l e 5 shows how a Pr oduc t Name number s the L ocal slots in r espons e to a T ype 0 or T ype 1 configu ration cycl e. The local bu s lines s_ad<2 4> and s_ad< 31:2 8 ...
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Intel 21555 - page 13
21555 PCI -to-PCI Bridge Ev aluation Board User ’ s Guid e 13 Introduction 1.8 Interru pt Rou tin g Ta b l e 6 sh ows the ORing of interr upts. 12 interr upts are connected to each of three secon dary bus PCI slots but four (4 ) interr upts are dri ven to the card ed ge. The 1 2 incoming interrupts must be combined. In terrupt ORing is in accorda ...
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Intel 21555 - page 14
14 21555 PCI-to-P C I Br idge Evalua tion Board User ’ s Guide Introduction 1.9 T ypical Co nfigurations Figur e 5 shows the DE1B 55503 with on e local bus option card. The option card can be either 32-bit or 64-bi t. Figure 5. DE1B 55503 wit h One Loca l Bus Option Card A8412-01 ADD-IN CARD 21555 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 J7 J8 L2 L1+ ...
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Intel 21555 - page 15
21555 PCI -to-PCI Bridge Ev aluation Board User ’ s Guid e 15 Introduction Figur e 6 shows the DE1 B55503 wi th two lo cal bus opt ion cards. Figure 6. DE 1B55503 wit h T wo Local Bus Op tion Cards A8413-01 ADD-IN CARD 21555 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 J7 L2 L1+ ...
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Intel 21555 - page 16
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Intel 21555 - page 17
21555 PCI -to-PCI Bridge Ev aluation Board User ’ s Guid e 17 Operations and Installation 2 This chapter pr ovides DE1B 55503 specifi cations and inf ormation about the har dware and software requirements fo r using t he DE1B5550 3. It also describes how to inst all the DE1B 55503. 2.1 S pecifications This sectio ns describes some overall s pecif ...
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Intel 21555 - page 18
18 21555 PCI-to-P C I Br idge Evalua tion Board User ’ s Guide Operations and Installation • MSKROM.EXE an executable utility for programming the SROM. • The software diskettes ar e standard 3.5 inch floppy disks. Follow th e installation procedu re printed on the ins ide of the shipping package. Be certain th at the target sys tem meets the ...
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Intel 21555 - page 19
21555 PCI -to-PCI Bridge Ev aluation Board User ’ s Guid e 19 Operations and Installation 2.3.2.1 Board Setup Ta b l e 8 gives the DE1B55503 switch configu rati on for using th e DBFLASH.EXE utility . 2.3.2.2 Runni ng DbFl ash.ex e Make sure that both DBFLASH.EXE and DOS4GW .EXE are in the same directory or enviro nment path. The user must specif ...
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Intel 21555 - page 20
20 21555 PCI-to-P C I Br idge Evalua tion Board User ’ s Guide Operations and Installation connectors and one (1) conn ector-less slo t. Section 1.9, “ T ypical Confi guration s ” on pag e 14 shows examples of typical PCI configurations. 6. Apply power to the system. 7. V erify the auto-con figuratio n of the 2155 5 and oth er options . a. If ...
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Intel 21555 - page 21
21555 PCI -to-PCI Bridge Ev aluation Board User ’ s Guid e 21 Optional Configurations 3 3.1 PICMG Configurat ion This sectio n describ es how to configure the DE1B555 03 to hav e a Single B oard Compu ter (SBC) with a PCI interface as defined in the PICMG PCI-ISA Interface Specification. See Section 1.3.1, “ Connectors ” on page 6 . The DE1B5 ...
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Intel 21555 - page 22
22 21555 PCI-to-P C I Br idge Evalua tion Board User ’ s Guide Optional Configurations • In the other configuration, the central fun ctio n is controlled by the intelligent subsystem through th e J1 connector. Ta b l e 1 3 sh ows how th e req# and gn t # lines mu st be con figured fo r PICMG operation. 3.3 Asynchron ous Clockin g Ta b l e 1 4 s ...
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Intel 21555 - page 23
21555 PCI -to-PCI Bridge Ev aluation Board User ’ s Guid e 23 Signal and Default Information A A.1 J2 J4, J5, and J6 Co nnector Pinou ts Ta b l e A - 1 gives the Mictor connector s pin assignmen t and DE1B5550 3 schematic signal n ames. See Figu re 1 o n page 6 for the location of this connector . T able A-1. J2 Connector Secondary AD Signals Sch ...
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Intel 21555 - page 24
24 21555 PCI-to-P C I Br idge Evalua tion Board User ’ s Guide Signal and Default Information Ta b l e A - 2 gives the Mi ctor conn ectors pin assignment and DE1B55 503 schemat ic signal na mes. Tab le A- 3 gives the Mictor connectors pin assignment and DE1 B55503 schematic s ignal names. T able A-2. J4 P in Assignm ents Schema tic Signal Name Mi ...
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Intel 21555 - page 25
21555 PCI -to-PCI Bridge Ev aluation Board User ’ s Guid e 25 Signal and Default Information Table A-4 gives the Mictor connectors pin ass ignment and DE1B 55503 schematic signal names . S_REQ8 23 24 S_GNT1 S_REQ7 25 26 S_GNT0 S_REQ6 27 28 S_M66ENA S_REQ5 29 30 S_PNE S_REQ4 31 32 S_REQ3 33 34 S_CLKI S_REQ2 35 36 SCLK_O S_REQ1 37 38 T able A-4. J6 ...
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Intel 21555 - page 26
26 21555 PCI-to-P C I Br idge Evalua tion Board User ’ s Guide Signal and Default Information A.2 J A T AG Conn ector Pinout Ta b l e A - 5 gives the p in assign ments between the DE1B55 503 sch ematic and the ten-pi n JT AG connector . See Figure 1 on page 6 for the location of t his connector . A.3 Facto ry Default Switch and Jumper Con figurat ...
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