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Manual Xilinx UG492

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  • Xilinx UG492 - page 1

    LogiCORE TM IP Ethernet A VB Endpoint v2.4 User Guide UG492 July 23, 2010 ...

  • Xilinx UG492 - page 2

    Ethernet A VB Endpoint User Gu ide www .xilinx.com UG492 July 23, 2010 Xilinx is providing this product documentation, hereinafter “Inf or mation, ” to you “AS IS” with no warr anty of any kind , e xpress or implied. Xilinx makes no represen tation that the Inf or mation, or any part icular implementation thereof, is free from any claims of ...

  • Xilinx UG492 - page 3

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 3 UG492 July 23, 2010 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx UG492 - page 4

    4 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 4: Generating the Core Ethernet AVB GUI Page 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Component Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx UG492 - page 5

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 5 UG492 July 23, 2010 Chapter 8: Real Time Clock and Time Stamping Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 RTC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx UG492 - page 6

    6 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 14: Quick Start Example Desig n Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx UG492 - page 7

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 7 UG492 July 23, 2010 Chapter 16: Detailed Exam ple Design (EDK format) Directory and File Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 <project directory> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx UG492 - page 8

    8 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 ...

  • Xilinx UG492 - page 9

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 9 UG492 July 23, 2010 Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Overview of Ethernet Audio Video Bridging Figure 3-1: Example AVB Home Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 3-2: Example Ethernet AVB Endpoint System . ...

  • Xilinx UG492 - page 10

    10 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 9: Precise Timing Protocol Packet Buffers Figure 9-1: Tx PTP Packet Buff er Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 9-2: Rx PTP Packet Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx UG492 - page 11

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 11 UG492 July 23, 2010 Chapter 16: Detailed Exam ple Design (EDK format) Appendix A: RTC Time Stamp Accuracy Figure A-1: RTC Periodic Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure A-2: RTC Sampling Logic . . . . . . . . . . . . . . ...

  • Xilinx UG492 - page 12

    12 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 ...

  • Xilinx UG492 - page 13

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 13 UG492 July 23, 2010 Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Overview of Ethernet Audio Video Bridging Chapter 4: Generating the Core Table 4-1: XCO File Values an d Default Value s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Chapter 5: Core A ...

  • Xilinx UG492 - page 14

    14 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Table 10-7: Seconds Field Offset bits [ 31:0] (PLB_base_address + 0x2808) . . . . . . . . . . . . 95 Table 10-8: Seconds Field Offset bits [47: 32] (PLB_base_address + 0x280C) . . . . . . . . . . 95 Table 10-9: RTC Increment Value Control Regi ster (PLB_base_address + 0x2810) ...

  • Xilinx UG492 - page 15

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 15 UG492 July 23, 2010 Chapter 16: Detailed Exam ple Design (EDK format) Table 16-1: Project Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 16-2: Component Name Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx UG492 - page 16

    16 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 ...

  • Xilinx UG492 - page 17

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 17 UG492 July 23, 2010 Pr eface About This Guide The LogiCORE™ IP Ethernet A VB User Guide provides information about the Ethernet Audio V ideo Bridging (A VB) Endpoint core , including how to customize, generate, an d implement the core in supported Xilinx FPGA families. Guide Contents This guid ...

  • Xilinx UG492 - page 18

    18 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Pref ace: About This Guide • Chapter 13, “Software Drivers” describes the function of the software drivers deliver ed with the core. • Chapter 14, “Quick Start Example Design”C hapter 3, “Quick Start Exa mple Design” provides instructions to quickly generate th ...

  • Xilinx UG492 - page 19

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 19 UG492 July 23, 2010 Con ventions Online Document The following conventions ar e used in this document: Braces { } A list of items fr om which you must choose one or mor e lowpwr = { on | off } V ertical bar | Separates items in a list of choices lowpwr = { on | off } Angle brackets < > Use ...

  • Xilinx UG492 - page 20

    20 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Pref ace: About This Guide List of Abbre viations The following table describes acronyms used in this manual. Acron ym Spelled Out A V Audio V ideo A VB Audio V ideo Bridging BMCA Best Master Clock Algorithm CRC Cyclic Redundancy Check DA Destination Address DMA Direct Memory ...

  • Xilinx UG492 - page 21

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 21 UG492 July 23, 2010 Con ventions PHY physical-side interface PHY AD Physical Address PLB Processor Local Bus PTP Precise T iming Protocol REGAD Register Addr ess RT C Re a l Tim e C l o c k RO Read Only R/W Read/W rite Rx Receive SFD Start of Frame Delimiter SRP Stream Reservation Pr otocol TEMA ...

  • Xilinx UG492 - page 22

    22 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Pref ace: About This Guide ...

  • Xilinx UG492 - page 23

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 23 UG492 July 23, 2010 Chapter 1 Intr oduction This chapter introduces the core and provides r elated information including recommended desi gn experience, additional r esources, technical support, and how to submit feedback to Xilinx. The Ethernet A VB Endpoint core is a fully verified solution th ...

  • Xilinx UG492 - page 24

    24 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 1: Introd uction Recommended Design Experience Although the Ethernet A VB Endpoint cor e is a fully verified solution, the challenge associated with implementing a complete de sign varies depending on the configuration and functionality of the application. For best res ...

  • Xilinx UG492 - page 25

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 25 UG492 July 23, 2010 Feedbac k Document For comments or suggestions about this document, submit a W ebC ase fr om www .xilinx.com/support/clearexpress/websupport.htm/ Be sure to include the following information: • Document title • Document number • Page number(s) to which your comments r e ...

  • Xilinx UG492 - page 26

    26 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 1: Introd uction ...

  • Xilinx UG492 - page 27

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 27 UG492 July 23, 2010 Chapter 2 Licensing the Cor e This chapter provides instructions for obtaining a license key for the Ethernet A VB Endpoint core, which you must do before using the cor e in you r designs. The Ethernet A VB Endpoint core is pr ovided under the terms of the Xilinx Co re S ite ...

  • Xilinx UG492 - page 28

    28 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 2: Licensing the Core Full The Full license ke y is available when you purchase a license for the core and pr ovides full access to all core functionality both in simulation and in hardware, including: • Functional simulation support • Back annotated gate-level sim ...

  • Xilinx UG492 - page 29

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 29 UG492 July 23, 2010 Chapter 3 Overview of Ethernet Audio V ideo Bridging Figur e 3-1 illustrates a potential home network, cons isting of wired (eth ernet) and wireless components, which utilize the te chnology being defined by the IEEE802.1 Audio V ideo Bridging T ask Group. This illustrates po ...

  • Xilinx UG492 - page 30

    30 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 3: Overview of Ether net A udio Video Bridging T o understand the requirements of this netw ork, we must dif ferentiate between certain types of data: • Audio and V ideo streaming data , referred to in this document as A V traffic . Requires a good quality of service ...

  • Xilinx UG492 - page 31

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 31 UG492 July 23, 2010 A VB Specificat ions P802.1Qa v This specification defines the mechanism for queuing and forwardi ng A V traffic fr om a talker to a listener acr oss the network. This can involve se veral network hops ( network bridge devices that the data must pass thr ough). P802.1Qav is a ...

  • Xilinx UG492 - page 32

    32 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 3: Overview of Ether net A udio Video Bridging P802.1Qat This specification define s a Str eam Reservation Pr otocol (SRP) which must be used over the A VB network. Every listener that intend s to receive audio/video A V traffic fr om a talker must make a request to r ...

  • Xilinx UG492 - page 33

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 33 UG492 July 23, 2010 T ypical Implement ation Figur e 3-2 illustrates that the Ethernet A VB Endpoi nt core supports the two main types of data interfaces at the client side: 1. The A V traffic interface is intended for the Qual ity of Service audio/vi deo data. Illustrated are a number of audio/ ...

  • Xilinx UG492 - page 34

    34 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 3: Overview of Ether net A udio Video Bridging ...

  • Xilinx UG492 - page 35

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 35 UG492 July 23, 2010 Chapter 4 Generating the Cor e The Ethernet A VB Endpoint core is fully configurable using the CORE Generator™ software, which pr ovides a Graphical U ser In terface (GUI) for defining parameters and options. For help starting and using the CO RE Generator softwar e, see th ...

  • Xilinx UG492 - page 36

    36 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 4: Generating the Co re Component Name The component name is used as the bas e name of the output files generated for the cor e. Names must begin with a letter and must be composed fr om the following characters: a through z, 0 thr ou gh 9 and “_”. Core Deliv er y ...

  • Xilinx UG492 - page 37

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 37 UG492 July 23, 2010 Ethernet A VB GUI P ag e 2 Ethernet A VB GUI P age 2 Figur e 4-2 shows page 2 of the Ethernet A VB Endp oint GUI customization scr een. This page provide s options for configuring the “PLB Interface” of the cor e. This option is only requir ed when generating in the Stan ...

  • Xilinx UG492 - page 38

    38 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 4: Generating the Co re P arameter V alues in the XCO File XCO file parameter names and their values are identical to the names and values shown in the GUI. Ta b l e 4 - 1 shows the XCO file parameters and values and summar i zes the GUI defaults. The following is an e ...

  • Xilinx UG492 - page 39

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 39 UG492 July 23, 2010 Chapter 5 Cor e Ar chitectur e As described in Chapter 4, “Generating the Core” , the cor e can be generated in one of two formats, the functionality of which is descri bed in this chapter: • “Standard CORE Generator Format” (provided for the standar d ISE® softwar ...

  • Xilinx UG492 - page 40

    40 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Arc hitecture Standar d CORE Generator Format Figur e 5-1 illustrates th e functional blocks of the Ethernet A VB Endpoint core when it is generated in standard CORE Gener ator format. As illustrate d, this is intended to be connected to the LogiCORE IP T ri-Mo ...

  • Xilinx UG492 - page 41

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 41 UG492 July 23, 2010 EDK pcore Forma t EDK pcore Format Figur e 5-2 illustrates th e functional blocks of the Ethernet A VB Endpoint core when it is generated in EDK pcore format. As illustrated, th is is intended to be connected to the XPS LocalLink T ri-Mode Ethernet MAC. Each of the functi ona ...

  • Xilinx UG492 - page 42

    42 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Arc hitecture Functional Bloc k Description The following functional blocks described in the fo llowing sections are illustrated in Figur e 5-1 and Figure 5-2 . PLB Interf ace The core pr ovides a PLB version 4.6 interface as its configuration port to pr ovide ...

  • Xilinx UG492 - page 43

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 43 UG492 July 23, 2010 Functional Bloc k Description Tx Arbiter Data for transmission over an A V B network ca n be obtained from thr ee types of sources: 1. AV T r a f f i c . For transmission from the A V T raffic I/F of the cor e. 2. Precise T iming Protocol (PTP) Packets . Initiated by the soft ...

  • Xilinx UG492 - page 44

    44 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Arc hitecture Precise Timing Protocol Bloc ks The various hardw are Pr ecise T iming Pr otocol (PTP) blocks within the core pr ovide the dedicated har dware to implement the IEEE P802.1AS specification. However , the full functionality is only achieved using a ...

  • Xilinx UG492 - page 45

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 45 UG492 July 23, 2010 Functional Bloc k Description RT C A significant component of the PTP network wide timing synchron ization mechanism is the Real T ime Counter (RTC), which pr ovides the common time of the network. Every device on the networ k will maintain its own local versi on. The R TC is ...

  • Xilinx UG492 - page 46

    46 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Arc hitecture Software Driv ers Software Driver s are delivered with the E thernet A VB Endpoint core. These drive rs provide functions which utilize the dedicated har dwar e within the core for th e PTP IEEE P802.1AS specification. Functions include: • The B ...

  • Xilinx UG492 - page 47

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 47 UG492 July 23, 2010 Core Interfaces Core Interfaces All ports of the core are internal connections in FPGA fabric. All clock signals a r e inputs and no clock resources are used by the cor e . This enables clock circui try to be implemented external ly to the cor e netlist, pr oviding full flexi ...

  • Xilinx UG492 - page 48

    48 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Arc hitecture Legacy T raffic Interf ace Legacy T raffic T ransmitter P ath Signals Ta b l e 5 - 2 defines the core client-side legacy traf fic transmitter signal s. These signals are used to transmit data from the legacy client logic into the core. All si gnal ...

  • Xilinx UG492 - page 49

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 49 UG492 July 23, 2010 Core Interfaces A V T raffic Interf ace A V T raffic T ransmitter P ath Signals Ta b l e 5 - 4 defines the core client-side A V traffic trans mitter sign als, used to transmit dat a from the A V client logic into the core. All signals are synchr onous to the MAC transmitter c ...

  • Xilinx UG492 - page 50

    50 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Arc hitecture A V T raffic R eceiv er P ath Signals Ta b l e 5 - 5 d e f i n e s t h e c o re c l i e n t s i d e A V t r a ff i c re c e i v e r s i g n a l s , us e d b y t h e c o re t o t r a n s f e r data to the A V client . All signals ar e synchronous t ...

  • Xilinx UG492 - page 51

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 51 UG492 July 23, 2010 Core Interfaces MA C Receiver Interf ace These signals connect dir ectly to the identi cally named T ri-Mod e Ethernet MAC signals and are synchr onous to rx_clk MA C Management Interface This interface is only pr esent when the core is generated in “Standard CORE Gen erato ...

  • Xilinx UG492 - page 52

    52 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Arc hitecture Processor Local Bus (PLB) Interf ace The Proce ssor Local Bus (PLB) on the Ethernet Audio V ideo core is designed to be integrated directly in the Xilinx Embed ded Development Kit (EDK) wher e it can be easily integrated and connected to the suppo ...

  • Xilinx UG492 - page 53

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 53 UG492 July 23, 2010 Core Interfaces PLB Interf ace Ta b l e 5 - 9 defines the signals on the PLB bus. Fo r detailed information, see the IBM PLB specification. Sh aded r ows re present signals not used by this cor e; inputs are ig nored and outputs are tied to a constant. These signals ar e sync ...

  • Xilinx UG492 - page 54

    54 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Arc hitecture PLB_wrPendPri[0:1] Input Unused. PLB pending r e ad bus r e quest indicator . PLB_r eqPri[0:1] Input Unused. PLB r equest priority . Sl_addrAck Output Slave address acknowledge Sl_SSize[0:1] Output Slave data bus size. Sl_wait Output Slave wait in ...

  • Xilinx UG492 - page 55

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 55 UG492 July 23, 2010 Core Interfaces Interr upt Signals Ta b l e 5 - 1 0 defines the interrupt signals asserted by the core . All interr upts are acti ve high and are automati cally asserted. All interrupts, r equired by the “Softwar e Drivers” deliver ed with the cor e, are cleared by soft w ...

  • Xilinx UG492 - page 56

    56 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 5: Core Arc hitecture PTP Signals Ta b l e 5 - 1 1 defines the signals which ar e output from the cor e by the “Preci se T iming Protocol Blocks.” The se signals ar e provided for refer ence only and may be used by an application. For example, the 1722 P acket Mana ...

  • Xilinx UG492 - page 57

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 57 UG492 July 23, 2010 Chapter 6 Ethernet A VB Endpoint T ransmission As illustra ted in Figur e 5-1 , data for transmission over an A VB network can be obtained from thr ee types of sources: 1. AV T r a f f i c . For tr ansmission fr om the “Tx A V T raffic I/F” of the cor e. 2. Precise T imin ...

  • Xilinx UG492 - page 58

    58 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 6: Ethernet A VB Endpoint T ransmission Error F r ee Legacy F rame T ransmission Figur e 6-1 illustrates the timing of a normal frame transfer . When the legacy client initiates a frame transmission, it places the first column of data onto the legacy_tx_data[7:0] port ...

  • Xilinx UG492 - page 59

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 59 UG492 July 23, 2010 Tx A V T r affic I/F Errored Legacy F rame T ransmission The legacy_tx_underrun is provided to give full backwards compatibility between the Legacy T raf fic I/F and the client interface of the T ri- Mode Ethernet MAC. The legacy_tx_underrun provides a mechanism to inject an ...

  • Xilinx UG492 - page 60

    60 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 6: Ethernet A VB Endpoint T ransmission Figur e 6-3 illustrates the timing of a normal frame transfer . When the A V client initiates a frame transmission, it places the first column of data onto the av_tx_data[7:0] port and asserts a logic 1 onto av_tx_valid . After t ...

  • Xilinx UG492 - page 61

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 61 UG492 July 23, 2010 Tx Arbiter Tx Arbiter Ov er view As illustra ted in Figur e 5-1 , data for transmission over an A VB network can be obtained from thr ee types of sources: 1. AV T r a f f i c . For transmission from the A V T raffic I/F of the cor e. 2. Precise T iming Protocol (PTP) Packets ...

  • Xilinx UG492 - page 62

    62 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 6: Ethernet A VB Endpoint T ransmission Figur e 6-4 illustrates the ke y features of the credit based algorithm, which ar e: • The Tx Arbiter will schedule queued trans mission fr om the “Tx A V T raf fic I/F” if the algorithm is in cr edit (greater or equal to 0 ...

  • Xilinx UG492 - page 63

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 63 UG492 July 23, 2010 Tx Arbiter • During A V traf fic transmissi on, credit is r emoved at a rate defined by the sendSlope. • The hiLimit and lo Limit settings impose a fixed range on the possible values of credit. If the available cr edit hits one of thes e l imits, it will not exceed, but s ...

  • Xilinx UG492 - page 64

    64 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 6: Ethernet A VB Endpoint T ransmission hiLimit The general equation is: hiLimitValue = 2000 x idleSlopeValue In this general equation, the val ue of 2000 is obtained fr om the maximum number of bytes which may be pr esent in legacy frames (an Envelope frame as defined ...

  • Xilinx UG492 - page 65

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 65 UG492 July 23, 2010 Chapter 7 Ethernet A VB Endpoint Reception Rx Splitter The input to the Rx splitter (see Figure 5-1 ) is connected dire ctly to the client Receive (Rx) interface of the connected Ethernet MAC. Rece ived data fr om an A VB network can be of three types: • Precise T iming Pro ...

  • Xilinx UG492 - page 66

    66 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 7: Ethernet A VB Endpoint Reception Error F r ee Legacy Fr a m e R e c e p t i o n Figur e 7-1 illustrates the timing of a normal inboun d err or free frame transfer that has bee n accepted by the “Legacy MAC Header Filters” The legacy client must be pr epared to a ...

  • Xilinx UG492 - page 67

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 67 UG492 July 23, 2010 Rx Legacy T raff ic I/F Errored Legacy F rame Reception As illustra ted in Figur e 7-2 , rece ption of any frame in w hich the legacy_rx_frame_bad is asserted (in place of legacy_rx_frame_good) indicates that this frame must be discar ded by the Legacy client; it was either r ...

  • Xilinx UG492 - page 68

    68 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 7: Ethernet A VB Endpoint Reception Figur e 7-3 illustrates Legacy frame r e ception for an error fr ee fra me in which at least one of the eight individual MA C Header Filters obtained a match (filter number 3 is illustrated as having obtained the match in this exampl ...

  • Xilinx UG492 - page 69

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 69 UG492 July 23, 2010 Rx Legacy T raff ic I/F MA C Header Filter Configuration The MAC Header Filters can be enabled or disabled by using the “Rx Filtering Control Register .” This contains a Promiscuous Mode bit, wh ich: • when enabled allows all frames to be r eceived on the Legacy Rx T ra ...

  • Xilinx UG492 - page 70

    70 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 7: Ethernet A VB Endpoint Reception Single MA C Header Filter Usage Examples Full Destination Address (D A) Match The example illustrated in Figur e 7-4 shows a single MAC Header Filter (one of the eight provided) configur ed to filter on a Destination Address. In or d ...

  • Xilinx UG492 - page 71

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 71 UG492 July 23, 2010 Rx Legacy T raff ic I/F P ar tial Destination Address (D A) Match The example illustrated in Figur e 7-5 shows a single MAC Header Filter (one of the eight provided) configur ed to filter on a partial De stination Addr ess. In order for the frame to obtain a match, the initia ...

  • Xilinx UG492 - page 72

    72 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 7: Ethernet A VB Endpoint Reception VLAN Prior ity Match The example illustrated in Figur e 7-6 shows a single MAC Header Filter (one of the eight provided) configur ed to filter on frames co ntaining a VLAN tag wi th a VLAN Priority value of 1. Any Other Co mbinations ...

  • Xilinx UG492 - page 73

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 73 UG492 July 23, 2010 Rx A V T ra ffic I/F Rx A V T raffic I/F The signals forming the Rx A V T raffic I/F ar e defined in Ta b l e 5 - 5 . all signals are synchronous to the T ri-Mode Ethernet MAC receiver clock, rx_clk , which must always be qualified by the corresponding clock enable, rx_clk_en ...

  • Xilinx UG492 - page 74

    74 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 7: Ethernet A VB Endpoint Reception Errored A V T raffic Reception As illustra ted in Figur e 7-8 , rece ption of any frame in w hich the av_rx_frame_bad is asserted (in place of av_rx_frame_good) indicates that thi s frame must be discar ded by the A V client; it was ...

  • Xilinx UG492 - page 75

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 75 UG492 July 23, 2010 Chapter 8 Real T ime Clock and T ime Stamping This chapter considers two of the logical comp onents that are partially responsible for the A VB timing synchr onization protocol. • “Real T ime Clock” • “T ime Stamping Logic” These are both described in this chapter ...

  • Xilinx UG492 - page 76

    76 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 8: Real Time Clock and Time Stamping Conceptually , the R TC is not related to the fr equency of the clock used to incr ement it. A configuration register within the core pr ovides a configurable increment rate for this counter: this increment register , “R TC Increm ...

  • Xilinx UG492 - page 77

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 77 UG492 July 23, 2010 Real Time Clock R TC Implementation Increment of Nanoseconds Field Figur e 8-2 illustrates the implementati on used to create the R TC nanoseconds field. This is performed by the use of an impleme ntation specific 20-bit sub-nanoseconds field as illustrated . The nanoseconds ...

  • Xilinx UG492 - page 78

    78 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 8: Real Time Clock and Time Stamping There ar e two stages to the implementation: (Step 1) Controlled F requency R TC The R TC Increment V alue illustrated in Figur e 8-2 is set directly fr om the “R TC Increment V alue Control Register .” The upper 6 bits of th is ...

  • Xilinx UG492 - page 79

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 79 UG492 July 23, 2010 Time Stamping Logic Cloc k Outputs Based on the Sync hroniz ed RTC Nanoseconds Field The clk8k (8 kHz clock) output, derived from the Synchr onized RTC, is pr ovided as an output from the cor e. The synchronized R TC counter , unlike the contr olled frequency version, has no ...

  • Xilinx UG492 - page 80

    80 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 8: Real Time Clock and Time Stamping Time Stamp Sampling P osition of MA C F rames A time stamp value should be sampled at the beginning of the first symbol following the Start of Frame Delimiter (SFD) of the Ethernet MAC frame as seen on the PHY . This is illustra ted ...

  • Xilinx UG492 - page 81

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 81 UG492 July 23, 2010 IEEE1722 Real Ti me Clock Format Because the Xilinx T ri-Mode Ethernet MACs ha ve a known fixed latency , the time stamps taken can easily be translated into the equi valent GMII position to comply with the standard. This is performed in the s oftwa re drivers wher e t he MAC ...

  • Xilinx UG492 - page 82

    82 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 8: Real Time Clock and Time Stamping ...

  • Xilinx UG492 - page 83

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 83 UG492 July 23, 2010 Chapter 9 Pr ecise T iming Pr otocol Packet Buf fers This chapter considers two of the logical comp onents which ar e partly re spo ns ib le fo r t he A VB timing synchr onization protocol. • “Tx PTP Packet Buffer” • “Rx PTP Packet Buf fer” These are both describe ...

  • Xilinx UG492 - page 84

    84 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 9: Precise Timing Prot ocol P acket Buffer s Despite the logic and fo rmatting of each indi vidual PTP buffer being identical, the block RAM is pre-initialized at device configuration to hold template copies of each of the PTP frames, as indicated in Figure 9-1 . This ...

  • Xilinx UG492 - page 85

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 85 UG492 July 23, 2010 Rx PTP P a c ket B uffer Rx PTP P acket Buff er The Rx PTP packet buf f er is illustrated i n Figur e 9-2 . This provides working memory to hold each received PTP frame. The soft ware drivers, via the PLB configurati on bus, can then read and decode the contents of the r ecei ...

  • Xilinx UG492 - page 86

    86 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 9: Precise Timing Prot ocol P acket Buffer s The “Softwar e Drivers” provided with the core, using the PLB and dedicated interrupt, will use this interf ace to decode, and then act on, the received PTP packet information. X-Ref Target - Figure 9-2 Figure 9- 2: Rx P ...

  • Xilinx UG492 - page 87

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 87 UG492 July 23, 2010 Chapter 10 Configuration and Status This chapter provides general guidelines for config uring and monitoring the Ethernet A VB Endpoint core, including an introduction to the PLB configuration bus and a description of the core management r egisters. Pr ocessor Local Bus Inter ...

  • Xilinx UG492 - page 88

    88 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Sta tus X-Ref Target - Figure 10-1 Figure 10-1: Single Read T ransac tion PLB_RNW PLB_BE[0:7] PLB_size[0:3] PLB_type[0:2] PLB_abort PLB_ABus[0:31] PLB_PAValid SI_wait SI_addrAck PLB_wrDBus[0:31] SI_wrDAck SI_wrComp PLB_wrBurst SI_rdDBus[0:31] SI_r ...

  • Xilinx UG492 - page 89

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 89 UG492 July 23, 2010 Proce ssor Local Bus Interface Single Write T r ansaction Figure 10- 2 illustrates a single write data tran sfer on the PLB. Note the following: • W ait states can be added to the Addr ess cycle by asserting Sl_wait a nd delayi ng Sl_addrAck . • W ait states can be i nser ...

  • Xilinx UG492 - page 90

    90 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Sta tus PLB Address Map and Register Definitions Figure 10- 3 displays an overview of the Addr es s Space occupied by the Ethernet A VB E n d p o i n t c o r e o n t h e P L B . C o m m o n a c r o s s a l l addr essable space, each unique PLB add ...

  • Xilinx UG492 - page 91

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 91 UG492 July 23, 2010 PLB Address Map and Register Definitions The entire address space is now described in two sections: • “Ethernet A VB Endpoint Add ress Space” • “T ri-Mode Ethernet MAC Addr ess Space” (which can be addressed thr ough the Ethernet A VB Endpoint core Addr ess Space) ...

  • Xilinx UG492 - page 92

    92 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Sta tus Ether net A VB Endpoint Address Space Rx PTP P ack et Buff er Address Space The Address space of the “Rx PTP Packet Buffer” is 4k bytes, fr om PLB_base_address to (PLB_base_addre ss + 0x0FFF). This r epresents the size of a single V ir ...

  • Xilinx UG492 - page 93

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 93 UG492 July 23, 2010 PLB Address Map and Register Definitions Rx PTP P ack et Control Register Ta b l e 1 0 - 2 defines the associated contr ol register of the “Rx PTP Packet Buffer ,” used by the “Software Drivers” to monitor the position of the mo st recently r eceived PTP frame.: Rx Fi ...

  • Xilinx UG492 - page 94

    94 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Sta tus Tx Arbiter Send Slope Control Register The sendSlope variable is define d in IEEE P802.1 Qav to be the ra te of change of credit, in bits per second, when the value of cr edit is decr easing (during A V packet transmission). T ogether with ...

  • Xilinx UG492 - page 95

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 95 UG492 July 23, 2010 PLB Address Map and Register Definitions This r egister and the r egisters defined in T able 1 0-6 and in Ta b l e 1 0 - 8 are linked. These three of fset values will be loaded into the RTC counter logic simultaneously following a write to the nanosecond of fset register defi ...

  • Xilinx UG492 - page 96

    96 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Sta tus This r egister and the r egisters defined in Ta b l e 1 0 - 1 1 and in Ta b l e 1 0 - 1 2 are linked. Whe n this nanoseconds value r egister is read, the entir e RTC (including the seconds field) is sampled. Ta b l e 1 0 - 1 1 describes th ...

  • Xilinx UG492 - page 97

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 97 UG492 July 23, 2010 PLB Address Map and Register Definitions Phase Adjustment Register Ta b l e 1 0 - 1 4 describes the Phase Adjustment Re gister , which has units of nanoseconds. This value is used to correct the 8k clock generati on cir cuit when a new na nosecond offset value is written to t ...

  • Xilinx UG492 - page 98

    98 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Sta tus MA C Header Filter Configuration When the core is ge nerated in “EDK pcore Format” , the “Leg acy MAC Header Filters” ar e not included since the xps_ll_temac can optionally contain its own Addr ess Filter logic. When not provide d ...

  • Xilinx UG492 - page 99

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 99 UG492 July 23, 2010 PLB Address Map and Register Definitions PLB_base_address + 0x3000 + (filter# * 0x20) + 0xC 0x00000000 R/W Match Pattern: Ethe rnet frame bits 96 to 127 32 bit pattern to matc h against the Ethernet frame bits 96 to 127. For frames with a VLAN tag, mat ch pattern bits[31:0] c ...

  • Xilinx UG492 - page 100

    100 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Sta tus T ri-Mode Ether net MA C Address Space When the core is generated in “EDK pcore Format” for import into EDK and connection to the xps_ll_temac, the address space defined in this section is not included and the address space will retur ...

  • Xilinx UG492 - page 101

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 101 UG492 July 23, 2010 PLB Address Map and Register Definitions MA C MDIO Registers The T ri-Mode Ethernet MAC has MDIO master capability . T o access an MDIO re gister via the Ethernet MAC, construct the address as follows: MDIO register address = PLB_base_add ress + 0x6000 + (MDIO_ADDRESS *8) wh ...

  • Xilinx UG492 - page 102

    102 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 10: Configuration and Sta tus ...

  • Xilinx UG492 - page 103

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 103 UG492 July 23, 2010 Chapter 1 1 Constraining the Cor e This chapter defines the Ethernet A VB Endp oint core constraints. An example user constraints file (UCF) is pr ovi ded fo r the core and the HDL example design. Required Constraints De vice, P ackage, and Speedgr ade Selection The Ethernet ...

  • Xilinx UG492 - page 104

    104 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 11: Constraining the Core PERIOD Constraints f or Clock Net s PLB_clk The clock provided to PLB_clk must be constrained to the appr opriate frequency . Note the frequency range of the embedded processor to which this bus is connected. For example, the maximum clock sp ...

  • Xilinx UG492 - page 105

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 105 UG492 July 23, 2010 Required Constraints r tc_clk The R TC can be incr emented from any available clock fr equency that is gre ater than the A VB standards defined minimum of 25 MHz. However , the faster the fr equency of the clock, the smaller will be the step incr em ent and the smoother will ...

  • Xilinx UG492 - page 106

    106 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 11: Constraining the Core INST "*top/rx_rtc_sample_inst/sample _taken_toggle" TNM = FFS "rx_sample_taken"; INST "*top/rx_rtc_sample_inst/resync _sample_taken_toggle/data_sync" TNM = FFS "rx_sample_taken_resync"; TIMESPEC "t ...

  • Xilinx UG492 - page 107

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 107 UG492 July 23, 2010 Required Constraints INST "*top/avb_configuration_inst/vl an_priority_a_int*" TNM = FFS "vlan_priority_a"; INST "*top/rx_splitter_inst/vlan_pri ority_a_sample*" TNM = FFS "vlan_priority_a_sample"; TIMESPEC "ts_vlan_priority_a_samp ...

  • Xilinx UG492 - page 108

    108 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 11: Constraining the Core INST "*top/avb_configuration_inst/tx _send_frame*" TNM = FFS "tx_regs_sample"; INST "*top/avb_configuration_inst/tx _sendslope_int*" TNM = FFS "tx_regs_sample"; INST "*top/avb_configuration_inst/tx ...

  • Xilinx UG492 - page 109

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 109 UG492 July 23, 2010 Required Constraints INST "*top/rtc_inst/rtc_configuratio n_inst/reg_nanosec_offset*" TNM = FFS "rtc_regs_sample"; INST "*top/rtc_inst/rtc_configuratio n_inst/reg_sec_offset*" TNM = FFS "rtc_regs_sample"; INST "*top/rtc_inst/rtc_c ...

  • Xilinx UG492 - page 110

    110 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 11: Constraining the Core INST "*top*generic_host_if_inst/host _toggle_reg2" TNM = FFS "host_toggle"; INST "*top*generic_host_if_inst/resy nc_host_toggle/data_sync" TNM = FFS "resync_host_toggle"; TIMESPEC "ts_host_toggle&q ...

  • Xilinx UG492 - page 111

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 111 UG492 July 23, 2010 Chapter 12 System Integration As described in Chapter 4, “Generating the Core” and Chapter 5, “Core Ar chitectur e” , the core can be generated in one of two formats: • “Standard CORE Generator Format” This option will deliver the core in the st andard CORE Gen ...

  • Xilinx UG492 - page 112

    112 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integrat ion LogiCORE IP T r i-Mode Et her net MA C (Soft Core) T r i-Mode Ether net MA C Core Generation When generating the T ri-Mode Ethernet MAC (TEMAC) cor e in the CORE Generator software, be sur e that the fo llowing options are selected: • Managem ...

  • Xilinx UG492 - page 113

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 113 UG492 July 23, 2010 Using the Xilinx LogiCORE IP T ri-Mode Ethernet MA Cs Connections Without Ether net Statistics Figure 12- 1 illustrates the connection of the Ethernet A VB Endpoint core to the Xilinx T ri- Mode Ethernet MAC (TEMAC) cor e when no t using the Ethernet Statistics core. Figure ...

  • Xilinx UG492 - page 114

    114 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integrat ion Because the TEMAC cor e can often be used in di fferent clocking modes, note the following: • The Ethernet transmitter client clock do main must always be connected to the tx_clk input of th e Ethernet A VB Endpoint cor e. Additionall y , the ...

  • Xilinx UG492 - page 115

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 115 UG492 July 23, 2010 Using the Xilinx LogiCORE IP T ri-Mode Ethernet MA Cs Connections Including Ether net Statistics Figure 12- 2 illustrates the connection of the Ethernet A VB Endpoint core to the Xilinx T ri- Mode Ethernet MAC (TEMAC) cor e when using the Ethernet Statistics core. This shar ...

  • Xilinx UG492 - page 116

    116 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integrat ion LogiCORE IP Embedded T r i-Mode Ether net MA Cs Vir te x-5 FPGA Embedded T r i-Mode Ether net MA C Wrapper Generation When generating the V irtex-5 FPGA Embedd ed Ethern et MAC W rapper (EMAC) in the CORE Generator softwar e, be sure that the f ...

  • Xilinx UG492 - page 117

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 117 UG492 July 23, 2010 Using the Xilinx LogiCORE IP T ri-Mode Ethernet MA Cs Connections Without Ether net Statistics Figure 12- 3 illustrates the connection of the Ethernet A VB Endpoint core to the Xilinx T ri- Mode Ethernet MAC (EMAC) cor e when no t using the Ethernet Statistics cor e. Figure ...

  • Xilinx UG492 - page 118

    118 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integrat ion Because the EMAC core can often be used in dif ferent clocking modes, note the following: • The Ethernet transmitter client clock do main must always be connected to the tx_clk input of th e Ethernet A VB Endpoint cor e. Additionall y , the t ...

  • Xilinx UG492 - page 119

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 119 UG492 July 23, 2010 Using the Xilinx LogiCORE IP T ri-Mode Ethernet MA Cs Figure 12- 4 illustrates the connection of the Ethe rnet A VB Endpoint core to the EMAC when using the Ethernet Statistics core. This share s much in common with Figur e 12-2 ; however , note the following additional poin ...

  • Xilinx UG492 - page 120

    120 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integrat ion X-Ref Target - Figure 12-5 Figure 12-5: Connection of the Ethernet A VB Endpoint Core into an Embedded Pr ocessor Sub-system Micro b l a ze BRAM xp s _intc xp s _ ua r tlite lm b _ b r a m_if_cntlr Ethernet AV B Endpoin t TEMAC C us tom A V log ...

  • Xilinx UG492 - page 121

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 121 UG492 July 23, 2010 Using the Xilinx LogiCORE IP T ri-Mode Ethernet MA Cs Figure 12- 5 can be implemented using the Xilinx tool set using two methods: • “Using an EDK Project T op Lev el” • “Using an ISE Software T op-Level Pr oject” Using an EDK Project T op Lev el Figure 12- 6 sho ...

  • Xilinx UG492 - page 122

    122 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integrat ion In t hi s e x am p le , t h e i ns ta n ce o f t he Et h er n et A VB E nd po i nt c ore sh o ul d be as s ig ne d a b as e address in the Micropr ocessor Hardwar e Specif ication (. mhs) file, to match that of the Ethernet A VB Endpoint “PLB ...

  • Xilinx UG492 - page 123

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 123 UG492 July 23, 2010 Using the Xilinx LogiCORE IP T ri-Mode Ethernet MA Cs Figure 12- 7 shows the implementation using an ISE® software top- level pr oject. In this hierarchy , the embedded processor subsyste m is created using an EDK pr oject containing only the blocks illustrated in the EDK t ...

  • Xilinx UG492 - page 124

    124 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integrat ion Using the Xilinx XPS LocalLink T ri-Mode Ethernet MA C The Ethernet A VB Endpoint core shoul d be generated in the “EDK pcore Format” when connecting to the XPS LocalL ink T ri-Mode Ethernet MAC core (xps_ll_temac). Introduction The xps_ll_ ...

  • Xilinx UG492 - page 125

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 125 UG492 July 23, 2010 Using the Xilinx XPS LocalLink T ri-Mode Ethernet MA C System Ov er view: A VB capable xps_ll_temac X-Ref Target - Figure 12-8 Figure 12-8: Connection of the Ethernet A VB Endpoint Core into an Embedded Pr ocessor Sub-system Micro b l a ze BRAM xp s _intc xp s _ ua r tlite l ...

  • Xilinx UG492 - page 126

    126 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integrat ion Figure 12- 8 illustrates the connection of th e core to an embedded pr ocessor subsystem (MicroBlaze™ pr ocessor is illustrated). Observe that: • The PLB can be shar ed across all peripherals as illustrated. • The “Interr upt Signals” ...

  • Xilinx UG492 - page 127

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 127 UG492 July 23, 2010 Using the Xilinx XPS LocalLink T ri-Mode Ethernet MA C MHS File Syntax The following code extracts are taken fr om an XPS pr oject which connected the Ethernet A VB Endpoint core to an instance of the xps_ ll_temac. This design tar geted the V irtex-5 family and implemente d ...

  • Xilinx UG492 - page 128

    128 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integrat ion BEGIN xps_ll_temac PARAMETER INSTANCE = Hard_Ethernet_ MAC PARAMETER C_NUM_IDELAYCTRL = 2 PARAMETER C_IDELAYCTRL_LOC = IDELAY CTRL_X0Y4-IDELAYCTRL_X1Y5 PARAMETER C_FAMILY = virtex5 PARAMETER C_PHY_TYPE = 1 PARAMETER C_TEMAC1_ENABLED = 0 PARAMET ...

  • Xilinx UG492 - page 129

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 129 UG492 July 23, 2010 Using the Xilinx XPS LocalLink T ri-Mode Ethernet MA C PARAMETER C_MEM0_HIGHADDR = 0xcc00f fff BUS_INTERFACE SPLB = mb_plb PORT reset = sys_periph_reset # Connect as per Figure 12-9 PORT tx_clk = Temac0AvbTxClk PORT tx_clk_en = Temac0AvbTxClkEn PORT rx_clk = Temac0AvbRxClk P ...

  • Xilinx UG492 - page 130

    130 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 12: System Integrat ion ...

  • Xilinx UG492 - page 131

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 131 UG492 July 23, 2010 Chapter 13 Softwar e Drivers Software d rivers deliver ed with the Ethernet A VB Endpoint core pr ovide the following functions, which utilize the dedicated ha r dwa re within the cor e for the Pr ecise T iming Protocol (PTP) IEEE P802.1AS specification: • Best Clock Maste ...

  • Xilinx UG492 - page 132

    132 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 13: Software Dr iver s Cloc k Slave If the core is acting as a clock slave , the local R TC is closely matched to the value and freque ncy of the network clock master . This is achieved, in part, by r eceiving the PTP Sync and Follow-Up frames transmitted across the n ...

  • Xilinx UG492 - page 133

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 133 UG492 July 23, 2010 Software Syst em Integrat ion For example, in the user softwar e, the A VB dr ivers can be instanced as follows: /* Allocate an instance of the XAvb device driver */ static XAvb Avb; int Status; XAvb_Config *AvbConfigPtr; . /* Initialize AVB Driver */ AvbConfigPtr = XAvb_Loo ...

  • Xilinx UG492 - page 134

    134 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 13: Software Dr iver s Core Initialization When Using a LogiCORE IP T r i-Mode Ether net MA C Note: When connecting to the XPS LocalLink T ri-Mode Ether net MAC (xps_ll_temac), av ailable in EDK, the MAC is delivered with its o wn dr ivers and t he functionality of th ...

  • Xilinx UG492 - page 135

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 135 UG492 July 23, 2010 Software Syst em Integrat ion Y ou should also update the following #define i f ther e is a known asymmetry in the propagation del ay on the link. This #def ine models the per -port global variable “delayAsymmetry” as defined in IEEE P802.1AS and should be edited based o ...

  • Xilinx UG492 - page 136

    136 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 13: Software Dr iver s * This function is the handler which will be called if the PTP drivers * identify a possible discontinuity in GrandMaster time. * This handler provides an example o f how to handle this situation - * but this function is application s pecific. * ...

  • Xilinx UG492 - page 137

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 137 UG492 July 23, 2010 Chapter 14 Quick Start Example Design The quick st art steps provided in t his chapte r let you quickly generate an Ethernet A VB Endpoint core, r un the design through implemen tation with the Xilinx tools, and sim ulate the design using the provi ded demonstration test ben ...

  • Xilinx UG492 - page 138

    138 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 14: Quick Start Example Des i gn The Ethernet A VB Endpoint example design ha s been tested using Xilinx® ISE® sof twar e v12.2, Cadence Incisive Enterprise Simulator (IES) v9.2, Mentor Graphics ModelSim v 6.5c, and Synopsys VCS and VCS MX 2009.12. X-Ref Target - Fi ...

  • Xilinx UG492 - page 139

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 139 UG492 July 23, 2010 Generating the Core Generating the Core This section pr ovides detailed instructi ons for generating the Ethernet A VB Endpoint example design core. T o g enerate the core: 1. Start the CORE Generator™ tool. For general help with st arting and using CORE Generator softwar ...

  • Xilinx UG492 - page 140

    140 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 14: Quick Start Example Des i gn X-Ref Target - Figure 14-2 7. Enter a core instance name in the Component Name field. 8. Maintain the default options on GUI page 1 so that Standard CORE Generator format is selected. 9. Click Generate to deliver the core using the def ...

  • Xilinx UG492 - page 141

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 141 UG492 July 23, 2010 Implementing th e Example Design Implementing the Example Design After the core is generated, the netlists and example design can be processed by the Xilinx implementation tools. The generated output fi les include several scripts to as sist you in running the Xilinx softwar ...

  • Xilinx UG492 - page 142

    142 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 14: Quick Start Example Des i gn Timing Simulation This section contains instructions for r unnin g a timing simulation of the Ethernet A VB Endpoint core using either VHDL or V erilog . A timing simulation model is generated when run through the Xilinx tools using th ...

  • Xilinx UG492 - page 143

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 143 UG492 July 23, 2010 Chapter 15 Detailed Example Design (Standard Format) This chapter provides detailed information about the core when generated for the St an da rd C OR E G en er at or™ s oft wa re f or ma t. Th is option is selected fr om page 1 of the customization GUI and will deli ver t ...

  • Xilinx UG492 - page 144

    144 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Stan dard Format) <component_name>/drivers/v2_04_a Files for compilin g the low-level d rivers pr ovided with the core drivers/avb_v2_04_a/data Data files for automatic integrat ion into Xili nx Platform Studio drivers/avb_v2_04_a/ex ...

  • Xilinx UG492 - page 145

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 145 UG492 July 23, 2010 Directory and File Contents <project director y>/<component name> The <component name> directory contains the r elease notes file pr ovided with the core, which may include l ast-minute changes and updates. <component name>/doc The doc directory conta ...

  • Xilinx UG492 - page 146

    146 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Stan dard Format) <component name>/implement The implement directory contains the cor e implementation script files. rx_frame_checker .v[hd] An HDL file which is capable of receiving Ethernet frames at maximum line rate. This will ch ...

  • Xilinx UG492 - page 147

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 147 UG492 July 23, 2010 Directory and File Contents implement/results The results dir ectory is created by the implem ent script, after which the implement script resul ts are placed in the results d irec tory . <component name>/simulation The simulation directory and subdir ectories that pro ...

  • Xilinx UG492 - page 148

    148 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Stan dard Format) simulation/timing The timing directory contains timing simulation scripts provided with the core. wave_ncsim.sv IES macro file that opens a wave window and adds signals of interest to it. It is called by the simulate_ncsi ...

  • Xilinx UG492 - page 149

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 149 UG492 July 23, 2010 Directory and File Contents <component_name>/dr iv ers/v2_04_a A directory containing the softwar e device dr ivers for the Ethernet A VB Endpoint core and associated supporting files. dr iv ers/avb_v2_04_a/data The driver data dir ectory contains the data file s for a ...

  • Xilinx UG492 - page 150

    150 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Stan dard Format) dr iv ers/avb_v2_04_a/src The driver source (sr c) directory contains the low-level driver source C files. T able 15- 12: Driver Sour ce Directory Name Description <project_dir>/<component_name>/driver s/ avb_ ...

  • Xilinx UG492 - page 151

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 151 UG492 July 23, 2010 Implementati on Scripts Implementation Scripts The implementation script is either a shell sc ript or batch file that pr ocesses the example design through the Xilinx tool flow and is one of the following locations: Linux <project_dir>/<component_name>/imple ment ...

  • Xilinx UG492 - page 152

    152 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Stan dard Format) Timing Simulation The test script is a ModelSim, IES, or VCS ma cr o that automates the simulation of the test bench and is in the following location: <project_dir>/<component_name>/simul ation/timing/ The tes ...

  • Xilinx UG492 - page 153

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 153 UG492 July 23, 2010 Example Desi gn T op-Le v el Example Design HDL The following files describe the top-level e xample design for the Ethernet A VB Endpoint core. VHDL <project_dir> / <component_name> /examp le_design/ <component_name>_example _design.vhd Ve r i l o g <pro ...

  • Xilinx UG492 - page 154

    154 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Stan dard Format) The data field of the frame is designed to cr ea te a simple 8-bit binary counter that cont inues seamlessly acr oss consecutive Ethernet fr am es. The Ethernet Frame Stimulus block is designed to produce frames at full l ...

  • Xilinx UG492 - page 155

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 155 UG492 July 23, 2010 Example Desi gn PLB Module The following files describe the logic for the PLB module. VHDL <project_dir> / <component_name> /examp le_design/ plb_client_logic.vhd Ve r i l o g <project_dir> / <component_name> /examp le_design/ plb_client_logic.v The P ...

  • Xilinx UG492 - page 156

    156 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Stan dard Format) Demonstration T est Bench Figure 15- 2 illustrates the Ethernet A VB Endpoint demonstration test bench, a simple VHDL or V e rilog progr am for exercising the example design and the core. The following files describe the ...

  • Xilinx UG492 - page 157

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 157 UG492 July 23, 2010 Example Desi gn Customizing the T est Bench Simulation Run Time The default simulation run time is set to only 40 micr oseconds, which can be easily extended by editing the simulation_run_time constant, set near the top of the demonstration test bench file. For example, from ...

  • Xilinx UG492 - page 158

    158 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 15: Detailed Example Design (Stan dard Format) Vie w ing the Simulation W av e Fo r m The Simulation S cripts for the selected simulator automati cally selects signals of inte rest from within the DUT and adds them to the simulator wave window . These ar e organized i ...

  • Xilinx UG492 - page 159

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 159 UG492 July 23, 2010 Chapter 16 Detailed Example Design (EDK format) This chapter provides detailed information abou t the cor e when generated in the Standar d Embedded Development Kit (EDK) format, in cludin g a description of files and the directory str ucture generated. This option is select ...

  • Xilinx UG492 - page 160

    160 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 16: Detailed Example De sign (EDK format) Directory and File Contents The core d irector ies and their associated files are defined in the foll owing tables. <project director y> The project dir ectory contains all the CO RE Generator softwar e project files. &l ...

  • Xilinx UG492 - page 161

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 161 UG492 July 23, 2010 Directory and File Contents <component name>/doc The doc directory contains the PDF documentation provided with the core . <component name>/MyProcessorIPLib This is the route directory which should be imported into the Xilinx Embedded Development Kit. MyProcessor ...

  • Xilinx UG492 - page 162

    162 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 16: Detailed Example De sign (EDK format) pcores/eth_a vb_endpoi nt_v2_04_a/hdl/vhdl Contains a VHDL wrapper file for the core netlist to enable integration into Platform Stud io. pcores/eth_a vb_endpoint_v2_04_a/netlist The pcore netlist dir e ctory contains the netl ...

  • Xilinx UG492 - page 163

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 163 UG492 July 23, 2010 Directory and File Contents dr iv ers/avb_v2_04_a/data The driver data dir ectory contains the data file s for automatic generation of paramet er specific files when integrated into Platform Studio. dr iv ers/avb_v2_04_a/e xamples The driver examples dir ectory contains an a ...

  • Xilinx UG492 - page 164

    164 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 16: Detailed Example De sign (EDK format) dr iv ers/avb_v2_04_a/src The driver source (sr c) directory contains the low-level driver source C files. T able 16- 9: Driver Sourc e Directory Name Description <project_dir>/<component_name>/MyPr ocessorIPLib/dr ...

  • Xilinx UG492 - page 165

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 165 UG492 July 23, 2010 Importing the Ethernet A VB Endpoint Core into the Embed ded Dev elopment Kit (EDK) Impor ting the Ethernet A VB Endpoint Core into the Embedded Development Kit (EDK) Y ou can import a generated Ethernet A VB En dpoint netlist into an EDK pr oject by following the usual step ...

  • Xilinx UG492 - page 166

    166 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Chapter 16: Detailed Example De sign (EDK format) ...

  • Xilinx UG492 - page 167

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 167 UG492 July 23, 2010 Appendix A R TC T ime Stamp Accuracy Time Stamp Accuracy The accuracy of the time stamps, taken by sampling the “Real T ime Clock” (R TC) whenever PTP frames ar e transmitted or received, is essential to the Pr ecise T iming Protocol acr oss the network link. For this re ...

  • Xilinx UG492 - page 168

    168 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Appendix A: R TC Time Stamp Accuracy The maximum R TC inaccuracy , per time stamp sa mple, is equ al to the period of th e R TC refer ence clock (in this example 40 ns). By using a high fr equency R TC refer ence clock, a high degree of accuracy can be obtained. X-Ref Target ...

  • Xilinx UG492 - page 169

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 169 UG492 July 23, 2010 Time Stamp Accuracy R TC Sampling Error It has to be assumed that the RTC r eference clock is of a differ ent frequency to the MAC transmitted and r eceiver clocks. There fore, the RTC sampling l ogic has to be asynchronous. There are a number of methods to obta in a time st ...

  • Xilinx UG492 - page 170

    170 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Appendix A: R TC Time Stamp Accuracy X-Ref Target - Figure A-3 Figure A-3: Sampling P osition Uncer tainty TIMING CA S E 1 MAC Tx/Rx clock toggle RTC Ref erence Clock Q0 Q1 Q2 T a ke R TC Sa mple clock b o u nd a ry MAC Tx/Rx clock toggle RTC Ref erence Clock Q0 Q1 Q2 T a ke ...

  • Xilinx UG492 - page 171

    Ethernet A VB Endpoint User Gu ide www .xilinx.com 171 UG492 July 23, 2010 Time Stamp Accuracy Accuracy Resulting from the Combined Errors The section “R TC Real T ime Instantaneous Error” describes how a maximum err or of one R TC reference clock per iod can r esult as a consequence of the R TC itself. The section “R TC Sampling Error” des ...

  • Xilinx UG492 - page 172

    172 www .xilinx.com Ethernet A VB Endpoint User Guide UG492 July 23, 2010 Appendix A: R TC Time Stamp Accuracy ♦ If the flip-flop samples the new value, then T iming Case 1 r esults. The R TC is sampled as 200 (resulting in an err or of 39 ns which is entirely due to the “R TC Real T ime Instantaneous Error” ). ♦ If the flip-flop samples th ...

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