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Manual Intel 80C196NU

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  • Intel 80C196NU - page 1

    8XC196NP, 80C196NU Mi c roc on t ro l ler  U ser ’ s M a nual ...

  • Intel 80C196NU - page 2

    8X C196NP , 80C196NU Micr oc o ntr oller User ’ s Manual Aug u s t 2004 Order Number 272479-00 3 ...

  • Intel 80C196NU - page 3

    ii Informa tion in thi s document is provide d sole ly to enabl e u se of In tel products. Intel a ssumes no liabi lity w hatsoever , incl udin g infringem ent of an y patent or copyrig ht, for sale and use o f Intel products except as provi ded in Inte l’s T erms and Co nditi ons of S ale for such products. Intel Corporation ma kes no warranty f ...

  • Intel 80C196NU - page 4

    iii CONT E NTS CHAPTER 1 GUIDE TO THIS MANUAL 1. 1 MANU AL C ONT ENTS ... ....... .......... ....... .......... ..... ....... .......... ....... .......... ....... ........ ....... . 1-1 1. 2 NOTATI ONAL CO NVEN TIONS AN D TE RMIN O LOGY ... ....... .......... ....... .......... ..... ...... 1-3 1. 3 REL ATED D OCU MEN TS ..... .......... ....... . ...

  • Intel 80C196NU - page 5

    8XC1 96NP, 80C196NU USE R ’ S MANUAL iv CHAPTER 3 ADVANCED MA TH FEATURES 3.1 ENHANCED MULTIPLICATION INSTRUCTIO NS . ....... . ........... . ......... . ........... ............ .. 3-1 3.2 OPERATING MODES ........ . ......... . ...... .......... . ........... . ...... .......... .......... . ........ ........ ......... 3-2 3.2.1 Saturatio n Mode ...

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    v CONTENTS 4.5.1 Using Registers . ...................................... ... .............. . ..................... ... ......................4-12 4.5.2 Addressing 32-bit Operands .. . ........... ... .............. ... ................... . ................ ............. 4-12 4.5.3 Addressing 64-bit Operands .. . ........... ... .............. .. ...

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    8XC1 96NP, 80C196NU USE R ’ S MANUAL vi CHAPTER 6 STANDARD AND PTS INTERRUPTS 6.1 OVERVIEW OF INTERRUPTS. . .... .. ........ . .... ....... .. ........ . .... . ...... .......... . ...... . .... . ...... ....... 6-1 6.2 INTERRUPT SIGNALS AND REGISTERS ......... . ......... ............ ................. . ......... . ........ 6-3 6.3 INTERRUPT SO ...

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    vii CONTENTS 7.3.1.4 Open - drain Outp ut Mode .. ................. . ........... . ......... . ........... ............ ................. . 7-14 7.3.1.5 Input Mode .. ....................................... . .. .. .................................. ... .. .. ... ............... 7-16 7.3.2 Configuring EPORT Pins ................... . ............. ...

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    8XC1 96NP, 80C196NU USE R ’ S MANUAL vi ii 10.2 EPA AND TIMER/CO UNTER SIGN ALS AND REGISTERS ..... . ......... ............ ............ 1 0-2 10.3 TIMER/COUNTER FUNCTIO NA L OVERVIEW............. . ................ ...................... ....... 1 0-5 10 .3.1 Cas cade Mode (Timer 2 Only) ................... ...................... .. ........... ...

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    ix CONTENTS 12.3 IDLE M ODE ............................................................................. .................................... 12-5 12.4 STANDBY MODE (80C196 NU ONLY) .... ............ . ......... ............ . ......... . ........... . ........... 12-6 12.4.1 Enab lin g an d Disabling Standby Mode ... . ........... . ......... . . ...

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    8XC1 96NP, 80C196NU USE R ’ S MANUAL x APPENDIX A INSTRUCTION SET REFERENCE APPENDIX B SIGNAL DESCRIPTIONS B.1 FUNCTIONAL GROUPINGS OF SIGNALS ............. ................. . ......... . ........... ............ . B-1 B.2 SIGNAL DE SCRIPTIONS ............ . ................ ...................... . ................ ..... ............ ..... ... ...

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    xi CONTENTS FIGURES Figure Page 2-1 8XC1 96NP and 80C196NU Block Diagram ...... ..... ....... ..... ....... ....... ..... ....... ...... . ........ . 2-2 2-2 Block Diagram of t he Core ............... . ......... ............ ................. . ......... . ........... ...............2-3 2-3 Clock Circui try (8XC19 6NP) ..... ..... . ...... ..... . ...

  • Intel 80C196NU - page 13

    8XC1 96NP, 80C196NU USE R ’ S MANUAL xi i FIGURES Figure Page 8-5 Serial Port Frames i n Mode 2 and 3 ...... ....... ....... ..... ....... ....... ...... . ...... ....... ....... ..... ......8-7 8-6 Serial Port Control (SP_CON) Register.................................................. ...................... 8-9 8-7 Serial Port Baud Rate (SP_BAUD ...

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    xiii CONTENTS FIGURES Figure Page 13-7 Chip Confi gur ation 1 (CCR1) Re gister .. . .......................... ... ......... ... ......................... 13-16 13-8 Multi plexing an d Bu s Width Options.................. . .............. . ................ . ................ . ..... 13-19 13-9 Bu s Activit y for F our Type s of Buses ..... . .... ...

  • Intel 80C196NU - page 15

    8XC1 96NP, 80C196NU USE R ’ S MANUAL xi v T ABLES T able Page 1-1 Han dbook s a nd P roduc t In for mation . ....... ............ ............... ............ ............ ............ ..... 1-6 1-2 A pplication Not es, Application Brief s, and Art icle Repr ints .................... ................. ..... 1-6 1-3 MCS ® 96 M icrocont roller Dat ...

  • Intel 80C196NU - page 16

    xv CONTENTS T ABLES T able Page 7-9 EPORT Pins . .... ........ ............ . .... ............ . ........ ........ .......... . ........ ........ ............ . .... ........ 7-11 7-10 EPORT Control and St atus Re gisters . ....... ...................... . ................ ........................ . 7-12 7-11 L ogic Table for EPORT i n I/O Mode... ...

  • Intel 80C196NU - page 17

    8XC1 96NP, 80C196NU USE R ’ S MANUAL xvi T ABLES T able Page A-4 PSW Flag Setting Sy m bols ............................... . ......... ... .. ... ......... ... ......... . ......... ... ...... A-5 A-5 Operand Variables . ......... . ......... . ........... . ........... . ......... . ........... . ......... ............ . ........... . . A-6 A-6 ...

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    1 Guide to This Manu al ...

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    1- 1 CH A PT ER 1 GUI DE TO THIS MANUAL This manual describes the 8XC196NP and 80C196NU embedded microcont rollers. It is int en d ed for use by both s oftware a nd hardware de signers fam iliar wi th the princ iples of mi croc ontroll ers. This chapte r descri bes w hat you’ll find in this ma n ual, lists other documents tha t ma y be u s eful, ...

  • Intel 80C196NU - page 21

    1-2 8XC1 96NP , 80C196 NU USER’S MANUAL Chapter 8 — Se rial I/O (SIO ) Por t — desc ribes the asynchronous/synchronous seri al I/ O (SIO) port a n d expla i ns how t o p rogra m i t. Chapter 9 —Puls e-wi dth Modul ator — provides a functional o verview o f t he puls e width mod- ulator (PWM ) mo dules, describes how to program them, and p ...

  • Intel 80C196NU - page 22

    1- 3 G UIDE TO THIS MANUAL 1.2 NO TATIO NAL CONV ENTI ONS AND T E RM INOLO GY The followi n g notations an d terminol ogy are used t hrou ghout this manua l. The Gl ossa r y defines other terms with special meaning s. # The po u nd symbol ( # ) has eithe r of two m e a nings, depending on the context. When use d wi th a signa l name, the symbol me ...

  • Intel 80C196NU - page 23

    1-4 8XC1 96NP , 80C196 NU USER’S MANUAL itali cs Italics i dentif y variables and i ntroduce new t ermi nolo gy . The context in which italics are used di stinguishes betwe en the t wo possible meani ngs. V ariable s in regist ers and signal names are commonl y repres ented by x and y , where x re prese nts t he fi rst varia ble an d y represent ...

  • Intel 80C196NU - page 24

    1- 5 G UIDE TO THIS MANUAL t Lowercas e “ t ” represents the internal opera t i ng period. See “Internal T iming” on page 2-7 for details. units of m easu re The foll owing a b brevia tio ns are use d t o repres ent unit s of mea sure: A a mp s, am per e s DCV direct curre nt vol ts Kb yte s kil o byt es kHz kilohert z k Ω kil o -ohms mA ...

  • Intel 80C196NU - page 25

    1-6 8XC1 96NP , 80C196 NU USER’S MANUAL T able 1- 1. Handb ooks and Pro duct Information Titl e and Des c riptio n Orde r Num be r I nte l Em be dd ed Qu i c k R e fe ren ce G u id e 27 24 39 S oluti on s for E m bedd ed Appl icat io ns Guide 24 06 91 D at a on D em a nd fact sh eet 24095 2 D at a on D em a nd a n nual subscription (6 issues; Win ...

  • Intel 80C196NU - page 26

    1- 7 G UIDE TO THIS MANUAL A P-44 5, 8XC19 6K R Pe rip he ral s: A Use r ’s Po int of View † 27 08 73 A P-44 9, A Compariso n of t he Event Processor Arra y ( EP A) and Hig h S peed Inp ut/Outp ut (HSI O) Un it † 27 09 68 A P-47 5, Usin g the 8 XC19 6NT †† 27 23 15 A P-47 7, Low Volta ge Em bed ded Desig n †† 27 23 24 A P-48 3, Appl i ...

  • Intel 80C196NU - page 27

    1-8 8XC196N P , 80C1 96NU USER ’S MA NUAL T abl e 1-5. M CS ® 96 M i crocon tr oller Quick R eferences Title and Des criptio n Ord e r Numbe r 8XC1 96KR Qu ic k Ref erence (includes th e JQ, JR, KQ, KR) 2721 13 8XC1 96KT Quick Re feren ce 27226 9 8XC1 96M C Qui ck Refe rence 2721 14 8XC1 96NP Qu i ck Ref erence 27246 6 8XC1 96NT Qu ick Ref ere n ...

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    1-9 G UIDE TO THIS MANUAL Page Intentionally Left Blank ...

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    1-10 8XC196N P , 80C1 96NU USER ’S MA NUAL Page Intentionally Left Blank ...

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    1-11 G UIDE TO THIS MANUAL 1.4 .4 World Wi de We b W e of fer a variety o f information throug h t he W orld W ide W eb (URL:http://www . intel.com/ ). Se- lec t “Embedded Design Prod uc ts” from the Intel home page. 1.5 T ECHNI CAL S UPPO RT In the U.S. a nd Cana da, technic al support representa tives are availabl e to a nswe r your que stio ...

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    2 Ar chit ectural Overview ...

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    2- 1 CH A PT ER 2 ARCHITECT URAL OVERV IEW The 1 6 -bit 8XC196NP an d 80C 196NU CHMOS microcontrollers are de signe d to h a ndle high- speed ca lcula tions and fast input/output (I/O) operatio ns. They share a common a rchitecture and instruct ion set wi th other me mbers of the MC S ® 96 mi crocontroller family . In addition t o thei r 16-bit ad ...

  • Intel 80C196NU - page 35

    8XC1 96NP , 80C196NU USER’S MANUAL 2-2 2.2 DE V ICE FE A T URES T able 2-1 l i st s t he features o f the 8XC1 96NP and 80C 1 96NU. 2.3 BLOCK DIA GR AM Figure 2-1 shows the ma jor blocks wit hin the devi ce. The core of the device (Figure 2-2) consi sts of the centra l p rocessing unit (C PU) and memory controlle r . The CPU co n t ains the regis ...

  • Intel 80C196NU - page 36

    2- 3 ARCHITECTURAL OVERVIEW Figure 2-2. Block Di agram of the Core 2.3.1 CP U Co ntro l The CPU is cont rolled by the microcode engi ne, which instructs the RAL U to perf orm operation s using bytes, words, or double words from either the 256-b y te lower register fi le or through a wi n- do w that di rec tl y a ccess es the u p per re gist er file ...

  • Intel 80C196NU - page 37

    8XC1 96NP , 80C196NU USER’S MANUAL 2-4 2.3.3 Regi ster Ari thmeti c-lo gic Uni t (RALU) The RAL U cont ains the microcode engine , the 16 -bit arit hmetic logic u nit (ALU), t he m aster pro - gram counter (PC), the processo r status word (PSW), a nd several re gist ers. The regist ers in the RALU are t he instr uction register , a co nstants reg ...

  • Intel 80C196NU - page 38

    2- 5 ARCHITECTURAL OVERVIEW 2.3.3.2 Instr uction Format MCS 96 m icroco ntrollers combi ne a large set of gene ral-purpose regis ters wi th a three - o perand instruct ion format. T h i s format allows a single inst ruction to spe c ify tw o source registers a nd a separat e desti nation regist e r . For exam ple, the followin g instructio n multip ...

  • Intel 80C196NU - page 39

    8XC1 96NP , 80C196NU USER’S MANUAL 2-6 The ext ended program co unter (EPC) i s an ext ensi on of the s lave PC. The E PC generates the up- per eight add r ess bits f or extended code fet ches and outputs them on the extende d addressing p ort (EPOR T). Because only four EPOR T pins are implement ed, only th e lower four address bits a re avail a ...

  • Intel 80C196NU - page 40

    2- 7 ARCHITECTURAL OVERVIEW 2.4 INTERNAL TIMING The clock circui try o f the 8XC1 96NP (Figure 2-3) is identical to that of earlier MCS 96 micro - controlle rs. It rec eives a n input c loc k signa l on XT AL1 provided by an exte rnal cryst al o r clock and divides the frequenc y b y two. The clock ge ne rat ors a ccept the divi ded i n put frequen ...

  • Intel 80C196NU - page 41

    8XC1 96NP , 80C196NU USER’S MANUAL 2-8 Figure 2-4. Cl ock Circuitry (80C196NU) For both the 8XC 196NP and 80C196NU, the rising edges of PH1 and PH2 generat e C LKOUT (Figure 2-5). T he clock circui try routes se parate inte rnal clock signa ls to the CPU and the periph- erals to provide flexibi lity in power managem ent. (“Re ducing P ower Cons ...

  • Intel 80C196NU - page 42

    2- 9 ARCHITECTURAL OVERVIEW Figure 2-5. Internal Clock Phases The combined peri od of phase 1 and ph ase 2 of t he internal CLKOUT sig nal defines the basic t ime unit kn own as a state time or st ate . T able 2-2 l ists state time durations at various frequencies. The followi n g formulas calcul ate the frequency of PH1 and PH2, the duration of a ...

  • Intel 80C196NU - page 43

    8XC1 96NP , 80C196NU USER’S MANUAL 2-10 Figure 2-6. Effect of Clock Mode on CLKO U T Frequenc y T a b le 2-3. Relationships Bet ween Input Frequency , Clock Mul tipl ier , and Stat e Time s F XTA L 1 (Fre quenc y on X T AL 1) PL LEN2 :1 M ult ipli er f (I npu t Fre qu ency to the Div id e-b y-two Circ uit) t (Cloc k Period ) Sta te Ti me 50 M H z ...

  • Intel 80C196NU - page 44

    2-11 ARCHITECTURAL OVERVIEW 2.5 INTERNAL P ERIPHERAL S The inte rnal periphe ral modules provide spec i al functio ns for a variety of appl ications. Thi s sec- tion provides a brief desc ript ion of t he periphera ls; su bsequent c ha pte rs descri be them in detail. 2.5.1 I/ O Ports The 8XC1 96 N P and 80C1 9 6NU have five I/O ports, por ts 1– ...

  • Intel 80C196NU - page 45

    8XC1 96NP , 80C196NU USER’S MANUAL 2-12 T imer 1 a nd ti mer 2 a re bot h 1 6-bit up/ down timer/ counte rs t hat can be c loc ked i nternall y o r ex - t ernall y . Each t im e r/ coun ter is ca lled a ti m er if it is clocked i nter nally and a count er if it is cl ock ed external ly . Se e Cha pter 10, “Event Proce ssor Arra y (EP A),” for ...

  • Intel 80C196NU - page 46

    2-13 ARCHITECTURAL OVERVIEW 2.6.2 T estin g the Prin ted Ci rcui t Board The on-circui t emula tio n (ONCE) mode elect rical ly isola tes the 8XC 1 96 device from the system. By in vokin g ON CE mode, you c an test the pri nted circuit board whil e the de vice is soldered onto the board. 2.7 DES IGN CONS IDERAT IONS FOR 80C196NP TO 80C196NU CONVE R ...

  • Intel 80C196NU - page 47

    8XC1 96NP , 80C196NU USER’S MANUAL 2-14 • The 80C 1 96NU’ s PWM has an a d di t ional pre scaler option (divide- b y-4), cont rolled by the PWM control regist er (CON_REG0). • When operating with a demul tiplexed bus, the 80C196NU can add an automa tic delay in the first cycl e followi ng a chip-sel ect change or i n a write c ycl e that fo ...

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    3 Advanced M ath Featur es ...

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    3- 1 CH A PT ER 3 ADVANCED MAT H FE ATURES The 80C196NU is the first member o f the MC S ® 96 m icroc ontroll er family to incorpo ra t e en- hanced 16-bit m ultiplication i nstr uct ions for pe r forming m ultiply -accumulat e operat ions and a dedicat ed, 32-bit ac cumul a tor register f or storin g the result s of these ope rations. The accum u ...

  • Intel 80C196NU - page 51

    8XC1 96NP , 80C196NU USER’S MANUAL 3-2 3. 2 OP ER A TI NG MO DE S The ac cumul ator has t wo opera tin g modes that all ow y ou to c o ntrol the resul ts of ope rations o n signed numbers. These modes are call ed saturati o n mo de and f ract ional m ode . 3.2.1 S aturation M od e Saturat ion occurs when the resul t of tw o posit ive numbe rs gen ...

  • Intel 80C196NU - page 52

    3- 3 ADVANCED MATH FEATURES 3.2.2 Fra ctio nal M od e A s igned fra ct iona l contai ns a n im aginar y deci ma l point be twe en t he si gn bit (the MSB ) and the adjac ent bit. Thes e example s illust rat e t he represe nta tion of 32-bit si g ned fractional numbers: 0 . 111 1111 1111 1111 1111 1111 1 111 1 111 0 .000 0000 0 000 0000 00 00 0 000 ...

  • Intel 80C196NU - page 53

    8XC1 96NP , 80C196NU USER’S MANUAL 3-4 3.3 ACCUMUL ATOR REG ISTER (ACC_0 x ) The 32-bit accumul ato r register (Figure 3-1) re si des at locations 0C–0FH. Read from or write t o the accum ula tor register as two w ords a t loca tio ns 0CH and 0EH. ACC_0 x x = 0 , 2 (8 0C1 96 N U) Add re ss : Rese t St ate: 0EH, 0 C H 00 H The 32 -b it accum u l ...

  • Intel 80C196NU - page 54

    3- 5 ADVANCED MATH FEATURES 3.4 ACCUM ULATO R CONTRO L AND STATUS REGIST ER (ACC_ST A T) The AC C_ST A T regis ter control s the opera ting mode and refl ec ts the status of the accum ula tor . The mode bits (FME and SME) are effective only f or s i g ned mult iplication. T able 3-2 describe s the 80C196NU’ s operat ion with e ac h of the four po ...

  • Intel 80C196NU - page 55

    8XC1 96NP , 80C196NU USER’S MANUAL 3-6 T able 3- 2. Effe ct of SME and FM E Bit Com binations SME F ME De scrip tion 0 0 Sets th e OVF a nd STOVF flag s if t he sign bits of the accum u lator and the adden d (the num be r to b e ad ded to the contents o f t he accum u la tor) are e qual , b ut the sig n bit o f the resu lt is th e op posite . 0 1 ...

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    4 Pr ogra mming Considerat ions ...

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    4- 1 CH A PT ER 4 PROG RAM MI NG CO NS IDE RAT IONS This se ction pr ovides an overvie w o f the inst ructio n set of the MCS ® 96 microcont rollers and of- fers guideli nes for program developme nt. Fo r detailed informa tion ab o ut spec ific instruct ions, se e Appendix A. 4. 1 OV ERVI EW OF T HE I NS TRUCTION SET The ins truct ion se t support ...

  • Intel 80C196NU - page 59

    8XC1 96NP , 80C196NU USER’S MANUAL 4-2 T able 4-2 lists the equivalent operand-type names for b oth C prog ramm ing a nd a sse mbly lan- gu age . 4.1.1 BIT O per and s A BI T is a singl e-bit vari abl e that ca n have t he B oole an va lues , “true” and “ fal se.” T he arc hitec - ture requi res that BIT s be a d d resse d as components o ...

  • Intel 80C196NU - page 60

    4- 3 PROGRAMMING CONSIDERATI ON S 4.1.4 WO R D Opera nds A WORD is an unsigne d, 16-bit vari able that can ta ke on va lues from 0 t h rough 65,535 (2 16 –1). Arithme tic and re lati onal op e rators can be a p plied to W ORD opera n ds, but the resul t must be in- t erp ret e d in mod ulo 65536 arith m e tic. Lo gic al operat ions on WOR Ds are ...

  • Intel 80C196NU - page 61

    8XC1 96NP , 80C196NU USER’S MANUAL 4-4 4.1.7 LO NG-IN TEGE R Ope rand s A LONG - INTEGE R is a 32-bit, signed va riable that can take on values from –2,147,483,648 (– 2 31 ) through +2,147,483 , 64 7 (+2 31 –1). The arc hitecture dire ctly supports LONG-INTEGER operands only a s the o p erand i n shi ft operat ions, a s the divi dend in 32- ...

  • Intel 80C196NU - page 62

    4- 5 PROGRAMMING CONSIDERATI ON S 4.1.1 1 Fl oati ng P oi n t Op erati on s The hardwa re does not dire ctly suppo rt o pera t ions on RE AL (floati ng point) variabl es. Those op- eratio ns are supported by floa ting point l ibrari es from third-party tool ve ndors. (See the De velop - ment T ools Handboo k .) The performance of these operations i ...

  • Intel 80C196NU - page 63

    8XC1 96NP , 80C196NU USER’S MANUAL 4-6 EST Extended store w ord . S tores t he val ue of the s ourc e (le ftm os t) word operand into the dest i natio n (r ightm ost) ope rand. This inst ruction allows y ou to move data from the lowe r register file to a nywher e in th e add ress s pace . It operates in extended i ndire ct and ext ended i ndexed ...

  • Intel 80C196NU - page 64

    4- 7 PROGRAMMING CONSIDERATI ON S 4.2.1 Dir ect Ad dre ssi ng Direct addres sing direc tly accesse s a loca tion i n the 256-byte lowe r regi ster fil e, wi thout i nvolv- ing the memory co ntroller . W i n dowing allow s you to rema p other sections of memory into the lower regist er fi le f or direc t acc ess (see Cha pter 5, “Me mory Partition ...

  • Intel 80C196NU - page 65

    8XC1 96NP , 80C196NU USER’S MANUAL 4-8 LD AX,[BX] ; AX ← MEM_WOR D(BX) ADDB AL,BL,[CX] ; AL ← BL + MEM_BYTE(CX) POP [AX] ; MEM_WORD(AX) ← MEM_WORD(SP) ; SP ← SP + 2 4.2.3.1 Extended Indirect Addressing Extended load an d st ore i nstruc tions can use indi rect a d d ressing. T he onl y difference is t hat the register containing the indi ...

  • Intel 80C196NU - page 66

    4- 9 PROGRAMMING CONSIDERATI ON S 4.2.3.4 Indir ect Addr e ssing with t he Stack Point er Y ou ca n also use i ndirect ad d re ssin g to acces s the to p of the s tack b y usi ng the stack po inter as the WO RD regist er in an indirect referenc e. The following inst ruct ion uses indirec t addressi ng with t he s tack poi nte r: PUSH [SP] ; duplica ...

  • Intel 80C196NU - page 67

    8XC1 96NP , 80C196NU USER’S MANUAL 4-10 ST AX,TABLE[BX] ; MEM_WORD(TABLE+BX) ← AX ADDB AL,BL,LOOKUP[CX] ; AL ← BL + ME M_BYTE(LOOKUP+CX) The inst r uction LD AX, T AB LE[B X] loads AX wi th t he co ntents of the me mory loc ation t hat re- sides at address T AB LE+B X. That is, the ins truction adds the c ontents of BX (the offset) to the con ...

  • Intel 80C196NU - page 68

    4-11 PROGRAMMING CONSIDERATI ON S 4.3 ASSEMBLY LANGUAG E ADDRE SSING M ODE SELECTIONS The assem bly l anguage simpl if i es the choice of addressin g modes . Use these features wherever p ossibl e. 4.3.1 Dir ect Ad dre ssi ng The asse mbly language chooses betwee n di rec t and zero-inde xed address ing dependi n g on the memory location of t he op ...

  • Intel 80C196NU - page 69

    8XC1 96NP , 80C196NU USER’S MANUAL 4-12 4.5.1 Usi ng Register s The 25 6-byte lower register file contains the CPU spec ial-funct ion registers and the s tack pointer . The remai nder of the lowe r regist er file and al l of the up per register fil e is avail able for your use. Perip heral special -func tio n regis ters (SFR s) and mem ory-m appe ...

  • Intel 80C196NU - page 70

    4-13 PROGRAMMING CONSIDERATI ON S 4.5.4 Li nki ng S u bro uti nes Parame te rs are pass ed t o s ubroutines via the st ac k. Para me ters are pushed into the stac k from the rightmost para met er to the left . The 8- bit parame te rs are pushe d into the stac k with the high-order byte undefined. T he 32-b it para met ers are pushed onto the stac k ...

  • Intel 80C196NU - page 71

    8XC1 96NP , 80C196NU USER’S MANUAL 4-14 4.6 SOF TW ARE PROTE CTI ON FEATU RES AND GUI DEL INES The device has seve ral feature s to assist in recoveri ng from h ardware and software errors. The un implemen t ed opcode int errup t provi des protection from executing unimple me nted opcodes. The hardware reset instruction (RST) can cause a reset if ...

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    5 Memory Part itions ...

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    5- 1 CH A PT ER 5 MEMO RY P ART ITIONS This chapte r descri bes the o rganizati on o f the ad dress spac e, i ts ma jor parti tio ns, and the 1-Mbyte and 64-Kbyte operating modes. 1-M byt e refers to the address spa ce define d by the 2 0 external address lines . In 1-M byte mode, c ode c an e xecut e from almost a nywhere in the 1-M byte spac e. I ...

  • Intel 80C196NU - page 75

    8XC1 96NP , 80C196NU USER’S MANUAL 5-2 Because t he four m ost-si gnifica nt bits (MSBs) o f the internal address can take any value s with out changi n g the external address, these four b its effec ti v e l y produce 1 6 copie s of th e 1-M by t e ad- dress spac e , for a tota l of 16 Mbytes in 256 pages, 00H–FFH (Figure 5-1). For example, pa ...

  • Intel 80C196NU - page 76

    5- 3 MEMORY PARTITI ONS Figure 5-2. Page s FFH and 00H 5.2 ME MO RY P ART IT ION S T abl e 5 -1 is a mem or y map of the 8XC 1 96NP a n d 80C196NU. The re mainder of this se ction de- scribes the partiti ons. FFFFFFH   FF3000H FF2FFFH    FF2080H FF207FH    FF2000H FF1FFFH         ...

  • Intel 80C196NU - page 77

    8XC1 96NP , 80C196NU USER’S MANUAL 5-4 T able 5-1. 8XC196NP and 80C196NU Memory Map He x Add ress De s crip tion Add res si ng Mode s FFF FFF FF 3000 Externa l device (m emory o r I /O) con nect ed to a ddress/da ta bu s In direct, inde xed , ext ended FF2 FF F FF 2080 Program mem ory (Note 1) Afte r a de vice rese t, the first in structi on fetc ...

  • Intel 80C196NU - page 78

    5- 5 MEMORY PARTITI ONS 5.2.1 E xternal Mem ory Several partitions in p ages 00H and FFH and all of pages 01H–0 EH ar e ass i gn ed to e xt ernal memory (see T able 5-1). Dat a can be stored in a ny part o f this memo ry . Instructions c an be sto red in any pa rt of this memory in 1-Mbyte mo d e , but can be stored only i n page F FH in 64-Kbyte ...

  • Intel 80C196NU - page 79

    8XC1 96NP , 80C196NU USER’S MANUAL 5-6 5.2.2.2 Special-pur pose Memory Special-purpose memor y resides in loc ations FF2000–FF207F H. It cont ains severa l rese r ved memory loc ations, the chip c o nfiguration byte s (CC Bs), and vec tors for both peri pheral transac- tion server ( P TS) a n d stan dard int errupts. Note tha t the s peci a l-p ...

  • Intel 80C196NU - page 80

    5- 7 MEMORY PARTITI ONS 5.2.2.3 Reserv ed Memory Lo cat ions Several memory locations are r e served for t esting or fo r use in future products. Do not read or write the se locat ions e xce pt t o i nit ia lize t hem t o the val ues shown in T able 5-3. The fun c tion or contents of t hes e locations ma y chan ge in future revis ions; software t h ...

  • Intel 80C196NU - page 81

    8XC1 96NP , 80C196NU USER’S MANUAL 5-8 T abl e 5-5. Per ipheral SFRs Reserve d Locatio ns EPORT SFRs Address High ( Odd) Byte Low ( Even) B y te Address High ( Odd) Byte Low (Even) Byte 1FEEH Reser ved Re served †† 1 FE6 H EP_ PI N Re ser ved 1FECH Reser ved Re served †† 1 FE4 H EP_ R EG Re ser ved 1FEAH Reser ved Re served †† 1 FE2 H ...

  • Intel 80C196NU - page 82

    5- 9 MEMORY PARTITI ONS NOTE Using any S FR as a base or index re gist er f or indirect or i ndexed o perati ons can cause unpredictable re sult s be caus e exte rnal e vents can c hange the cont ents of SF Rs . A lso, because som e S FR s a re c l eare d when read, co nsider the implicat ions of using an SFR as an operand in a read-m o d ify- writ ...

  • Intel 80C196NU - page 83

    8XC1 96NP , 80C196NU USER’S MANUAL 5-10 Figure 5-3. Register File Memor y Map T abl e 5-6 o n page 5-1 1 lists the regist er file memory addresses. The RAL U access es the lower registe r file directl y , wi t hout the use of the memo r y controller . It a lso acces ses a win d owed loca- tion direc tly (se e “Windowing” on pa ge 5- 13). Only ...

  • Intel 80C196NU - page 84

    5-11 MEMORY PARTITI ONS 5.2.4.1 Gene ral-pur pose Register RAM The lowe r registe r f ile c ontains ge neral -purpose regi ster RAM . The stack point er locations can also be u sed as general-purpose register RAM when stack operations are not be ing performed. The RA LU ca n acce ss thi s mem ory direc tl y , using direct ad dressi n g. The upper r ...

  • Intel 80C196NU - page 85

    8XC1 96NP , 80C196NU USER’S MANUAL 5-12 Subr outines may be nes t ed. Tha t is, each subroutine m ay c all ot her s ubroutines. T he CPU P USH- es the cont ent s o f t he program counte r ont o the stac k each time it e xecute s a subroutine call. The stack grows downward as entri es are added. The only limit to the nestin g depth is the am ount ...

  • Intel 80C196NU - page 86

    5-13 MEMORY PARTITI ONS 5.3 W I NDOW ING W indowing expands the amount of memory that i s a c c essible wi th direct ad dr essing. Dire c t ad- dressi ng can acc es s the lowe r regi ster fil e w ith sh ort, fast-e xec uti ng inst ructi ons. Wi t h window- ing, direct addressing ca n a lso acc ess the upper r e gis ter fi le and periphera l SFRs. W ...

  • Intel 80C196NU - page 87

    8XC1 96NP , 80C196NU USER’S MANUAL 5-14 5.3.1 S elec ting a Wi nd ow The wi ndow s election re gist er (Fig ure 5-5) has two functions. T he HLDE N bit (WSR .7) ena ble s and disables the bus-hold protocol (see Chapte r 13, “Interfac ing with Exte r nal Me mory”); it is unrelated to windowing. T he re maining bits select a window to be mapped ...

  • Intel 80C196NU - page 88

    5-15 MEMORY PARTITI ONS WS R1 (8 0C1 96 NU ) Address: Reset Sta te : 0015H 00H Wind ow sele ctio n 1 (WSR1 ) registe r selects a 32- o r 64-b yte segm e nt of t h e u pp er re g iste r file or peri phera l S FRs to be wi ndowe d i nto t he mid dle o f th e lower r eg ister file, be low a ny win dow sel ecte d by th e WSR. 7 0 80C1 96N U — W6 W5 W ...

  • Intel 80C196NU - page 89

    8XC1 96NP , 80C196NU USER’S MANUAL 5-16 5.3.2 Add ressi ng a L ocati on T hroug h a Wind ow After you ha ve sel ecte d the desired wi n dow , yo u need t o know the direct addres s of the m e mory locat ion (the address i n the lowe r r egist er file). For SFR s, refer to the W S R tabl es in Appen d i x C. For r egis ter file locat ions, cal cul ...

  • Intel 80C196NU - page 90

    5-17 MEMORY PARTITI ONS T able 5 -10. Win d ows Bas e Add ress (He x) WSR or WSR1 V al ue fo r 32 -by te Wind ow ( 00E0 –0 0FF H o r 00 60–0 07FH ) WSR or WSR1 V al ue fo r 64 -by te Win do w ( 00C0 –0 0F FH or 00 40 –007 FH) WSR Value fo r 128 -by te Win do w (0 080– 00FF H) P erip heral SFRs † 1FE0 † 7FH † 3F H † 1F H 1F C 0 7 E ...

  • Intel 80C196NU - page 91

    8XC1 96NP , 80C196NU USER’S MANUAL 5-18 Ap p endix C i ncl udes a table of the windowable SFRs wi th the window selection regis ter values and direct ad dresse s f or each win dow size . The followi ng examples explain h ow to determi ne the WSR value and d irect address for a n y windowable location. An additional exampl e sho w s ho w to set up ...

  • Intel 80C196NU - page 92

    5-19 MEMORY PARTITI ONS 5.3.2.4 Unsupported Locations Wi ndowing Example (8XC196NP Only) Assume that you wish to acc ess loca tion 1FE7H (the EP_PIN re gister , a mem ory-map ped SFR) with direct addressing through a 128-byte window . This loca ti on is i n the range of ad d resses (1FE0–1 FFFH) that cannot be windowed. Although y ou could set up ...

  • Intel 80C196NU - page 93

    8XC1 96NP , 80C196NU USER’S MANUAL 5-20 public function2 extrn ?WSR wsr equ 14h:byte sp equ 18h:word oseg var1: dsw 1 var2: dsw 1 var3: dsw 1 cseg function2: push wsr ;Prolog code for wsr ldb wsr, #?WSR ;Prolog code for wsr add var1, var2, v ar3 ; ; ; ldb wsr, [sp] ;Epilog code for wsr add sp, #2 ;Epilog code for wsr ret end ********************* ...

  • Intel 80C196NU - page 94

    5-21 MEMORY PARTITI ONS This l isti ng shows t he disa ssemble d code : 2080H ;C814 | PUSH WSR 2082H ;B14814 | LDB WSR,#48H 2085H ;44E4E2E 0 | ADD E0H,E2H,E4H 2089H ;B21814 | LDB WSR,[SP] 208CH ;6502001 8 | ADD SP,#02H 2090H ;F0 | RET 2091H ;C814 | PUSH WSR 2093H ;B14814 | LDB WSR,#48H 2096H ;44EAE8E 6 | ADD E6H,E8H,EAH 209AH ;B21814 | LDB WSR,[SP] ...

  • Intel 80C196NU - page 95

    8XC1 96NP , 80C196NU USER’S MANUAL 5-22 5.4 REM APPING INTERNAL ROM (83C196NP ONLY) The 83C196NP’ s 4 Kbyt es o f ROM are l ocated in FF2000– FF2FFFH. B y using t he RE MAP bit (CCB1.2) and t he E A# input, y o u c an a lso ac ce ss t hese loc ations i n ext ernal m emory (page 0FH or page 00H). The R EMA P bit is l oaded from C CB1 upon l ea ...

  • Intel 80C196NU - page 96

    5-23 MEMORY PARTITI ONS 5.5 FETCHI NG CODE AND DATA IN THE 1-MBYT E AND 64-KBYTE MO DES This sec ti on de scri bes how the devic e fetches i nstruct ions a n d acc ess es data in the 1-M byte and 64-Kbyte modes. W hen the devic e leaves rese t, the M ODE64 bit (CC B1. 1) selects the 1-M byte or 64-Kbyte mode. The mode ca nn ot be changed until t he ...

  • Intel 80C196NU - page 97

    8XC1 96NP , 80C196NU USER’S MANUAL 5-24 For nonextended instruct ions, the EP_R EG regist er provides the page number . Da ta and constant s in this page are call ed near data and near consta nts . NOTE The 8XC 1 96NP allow s you t o cha nge the va lue of E P_RE G t o c ontrol w hich memory pa ge a nonext ended inst ruction ac cesse s. Howeve r , ...

  • Intel 80C196NU - page 98

    5-25 MEMORY PARTITI ONS 5.5.3 Cod e Fetche s in the 1-Mbyte Mod e CCR1.1 (the MO DE64 bit) controls whether t he device operates in 1-Mb yte or 64-Kbyte mode. CCR1 is loaded with the conte nts of CCB1 at r ese t. When MODE64 is c l ear , t he dev ice opera tes in 1-Mbyte mode. In this mo d e , code c an execute from any page in the 1-M byte address ...

  • Intel 80C196NU - page 99

    8XC1 96NP , 80C196NU USER’S MANUAL 5-26 Code fetc hes are from external memo ry or i nte rnal me mory , d e pending on th e device , the m em- ory location, and the va lue of the EA# input. 80 C196NU: Code execut es fr om page 0FH in external me mory . (The 80C196NU has no E A# input.) 80 C196NP : For device s without internal nonv olatile memory ...

  • Intel 80C196NU - page 100

    5-27 MEMORY PARTITI ONS Data a cce sses t o 002000–002FFFH depend on the REMA P bit and the EA# input: • If remapping is disa ble d (CCB 1.2 = 0), acce sse s a re exte rnal . • If remapping is enabled ( CCB1.2 = 1), ac ce sses depen d on EA#: — If EA# is low , accesse s are ext ernal (REMA P i s ig nored). — If EA# is high, acce sse s a r ...

  • Intel 80C196NU - page 101

    8XC1 96NP , 80C196NU USER’S MANUAL 5-28 83C196NP only: Loca tions FF2000–FF2FFFH, w hich s tore code and spe cial-p urpose memo ry , are im plem ent ed by int ernal ROM . Data a cc ess es to locations FF2000–FF2FFFH a re di recte d to the flash mem o ry if EA# is low and to internal ROM if EA# is high. Loca tions FF2000–FF2FFFH can be re ma ...

  • Intel 80C196NU - page 102

    5-29 MEMORY PARTITI ONS 5.6.2 Exam ple 2: A 64-Kbyte System with Additi onal Data Storag e Figure 5- 10 s h ows anothe r syste m desi gned f or operation in the 64-Kbyte mode. Code exec ute s from pa ge F FH onl y . T his system is the same a s the e xample in “Exampl e 1: Usin g the 64-Kbyte Mo de” on page 5- 27, but with a dditional RAM . The ...

  • Intel 80C196NU - page 103

    8XC1 96NP , 80C196NU USER’S MANUAL 5-30 T able 5-1 3. Memory Map for the System in Figure 5-10 Add ress De sc rip tion FFF FFF H FF 3000 H Extern al fl ash mem ory (co de or fa r con st ants) FF2 FFF H FF 2080 H Prog ra m memory: 80 C19 6NP an d 8 0C1 9 6NU : Extern al flash m em ory 83C19 6N P : In terna l ROM (EA# = 1 ), e xter nal mem or y (EA ...

  • Intel 80C196NU - page 104

    5-31 MEMORY PARTITI ONS 5.6.3 E xampl e 3: Using 1-Mbyte Mo de Figure 5- 1 1 shows a syst em desi gned for operation in t he 1-Mbyt e mo de. In t his mo de, co de can execute fr om any page in the 1 -Mbyte m emory spa ce. The syste m uses both 8-bit and 16-bit buses and uses t he writ e-st r obe mode. (See Chapt er 13, “Interfac ing with External ...

  • Intel 80C196NU - page 105

    8XC1 96NP , 80C196NU USER’S MANUAL 5-32 T able 5 -14. Memory Map for the System in Fig ure 5- 1 1 Add ress De sc rip tion FFF FFF H FF 3000 H Extern al m em o ry (code o r fa r con stan t s) FF2 FFF H FF 2080 H Prog ra m memory: 80 C19 6NP an d 8 0C1 9 6NU : Extern al memo ry 83C19 6N P : In t ernal ROM (EA # = 1 ), e xtern al m emo ry (EA# = 0) ...

  • Intel 80C196NU - page 106

    6 Standard and P TS Interrupts ...

  • Intel 80C196NU - page 107

    ...

  • Intel 80C196NU - page 108

    6- 1 CH A PT ER 6 STANDARD AND PT S INTE RRUP TS This c hapter des cri bes the interrupt c ontrol ci rcuitry , priorit y scheme , and t iming for standa rd a nd peripheral transac tion se rver (P TS) inte rrup ts. It disc usse s the three s pecial i nte rr upts and the four P T S modes, two of whic h are used with the EP A to produce pul se-wi dth ...

  • Intel 80C196NU - page 109

    8XC1 96NP , 80C196NU USER’S MANUAL 6-2 Figure 6-1. Flow Diagram for PTS and Sta ndard I nterrupts No No PTS Enabled? PTSSEL. x  Bit = 1? Yes Yes No Interrupt Pending or PTSSRV Bit Set NMI Pending ? Interrupts Enabled ? Yes No Return INT _MASK. x  = 1? No Return Yes Return Reset INT_PEND. x  Bit Reset PTSSRV. x  Bit Prio ...

  • Intel 80C196NU - page 110

    6- 3 STANDARD AND PTS INTERRUPTS Figure 6-1 illust rates the interrupt p rocessing flow . In this fl ow diagram, “INT_M ASK” repre- sents both t he INT _MASK a nd INT_MA S K1 regi sters, and “INT_PEND” repre sents bot h the INT_PEND a nd INT_PEND 1 regi sters. 6.2 INTE RRUP T S IG NALS AND REG IST ERS T abl e 6-1 desc ribes the external int ...

  • Intel 80C196NU - page 111

    8XC1 96NP , 80C196NU USER’S MANUAL 6-4 6.3 INTE RRUP T S OURCE S AND P RI ORI TIES T able 6-3 lists the interrupts sources, their default priorit ies (30 i s h ighest and 0 i s lowe st), a nd their vec tor addres ses. The unimpl emente d opc ode and softwa re trap interrupts are not pri ori- tized; they go dire ctly to the i n te r rupt c ontroll ...

  • Intel 80C196NU - page 112

    6- 5 STANDARD AND PTS INTERRUPTS 6.3.1.1 Unimpleme nted Opcode If the CPU a ttem pts to execute an unimple me nted opcode, an indirec t vector through locat ion FF20 1 2H occurs . T his prevent s random software execut ion during hardware and software fail- ures. The interrupt vector should contai n the starting address of an error rout ine that wi ...

  • Intel 80C196NU - page 113

    8XC1 96NP , 80C196NU USER’S MANUAL 6-6 6.3.1.3 NMI The external NMI pin generat es a nonm aska ble interrupt for impl em ent at ion of c rit ical inter r upt routine s. NM I has the highest priorit y of all the priorit ized inte rrupts. It is passe d d irec t l y from the tra nsit i on de tector to the priorit y enc o der , and it ve cto rs indi ...

  • Intel 80C196NU - page 114

    6- 7 STANDARD AND PTS INTERRUPTS rupt if P T SSEL .5 is s et. T he i nter r upt vectors through F F2 04AH, but the corresponding en d -of- P T S interrupt vecto rs throug h F F200AH, the standard SIO transm i t interrupt vecto r . W hen the end-of - P TS interrupt vectors to the inte rrupt service routi ne, hardware clears the P TSSR V bit. The end ...

  • Intel 80C196NU - page 115

    8XC1 96NP , 80C196NU USER’S MANUAL 6-8 6.4.2 Cal culatin g Laten cy The maxi mum l atency occ urs when the interrupt request occurs too late f or acknowle dgment fol- lowin g the current i nstruct i on. The foll owing worst -case c alcul ation a ssum es that t he c urrent in- structi on is not a protec ted instruct i on. T o calcul ate latenc y , ...

  • Intel 80C196NU - page 116

    6- 9 STANDARD AND PTS INTERRUPTS Figure 6 -2. St andar d Int err upt Response T ime 6.4.2.2 PTS Int err upt Lat ency In both 64 -Kbyte and 1-Mbyte m od e s, t he maximum delay for a P TS in terrupt i s 43 s ta t e t i mes (4 + 39) a s shown in Figure 6-3. This delay time does not include t he added dela y if a p rotected instruct ion is b eing exe ...

  • Intel 80C196NU - page 117

    8XC1 96NP , 80C196NU USER’S MANUAL 6-10 6.5 PROG RAM MING THE I NTERRUP TS The P TS s elect re gister (P T SSEL) sel e cts eithe r P TS servic e or a stan dard so ftware interrupt s er- vice routine for each of the ma skabl e i nterrupt re que sts (see Fi gure 6-4). The int errupt ma sk reg- isters, INT_M ASK and INT_M AS K1, enable or disable (m ...

  • Intel 80C196NU - page 118

    6-11 STANDARD AND PTS INTERRUPTS 6.5.1 P rog ram mi ng Consi der atio ns for Mul tiplexed Inte rrup ts An overrun on the EP A ca pture compare channels can genera te the mult iple xed capture overrun interrupts (OVR0_1 a nd OVR2_3). W rite to the EP A_M ASK (Fig ure 10-1 1 on page 10-22) reg- ister to enable o r dis able the m ultipl exed interrupt ...

  • Intel 80C196NU - page 119

    8XC1 96NP , 80C196NU USER’S MANUAL 6-12 INT _MASK Address: Reset Sta te : 0008H 00 H The interru pt m ask (INT _MASK ) re giste r e nabl es o r d isab les (mas ks) i ndivid ua l int erru pt req u ests. (Th e EI and DI i nstru ct ions en ab le an d disab le se r vicing of a ll ma ska ble inte rrup ts.) INT _M ASK is the l ow by te of th e process ...

  • Intel 80C196NU - page 120

    6-13 STANDARD AND PTS INTERRUPTS 6.5.2 Modi fyin g Interru pt Prio rities Y our software can mo dify the de faul t priorit ies of maskable i nterr upts by control ling t he inter rupt mask registers (INT_M ASK and INT_M ASK1). For exampl e, you can specify whi ch interrupts, if any , can interrupt an inter ru pt ser vice r ou t in e. The foll owing ...

  • Intel 80C196NU - page 121

    8XC1 96NP , 80C196NU USER’S MANUAL 6-14 SERIAL_RI_ISR: PUSHA ; Save PSW, INT_MASK, INT _MASK1, & WSR ; (this disables all inte rrupts) LDB INT_MASK1, #010000 00B ; Enable EXTINT3 only EI ; Enable interrupt servic ing ; Service the RI interrup t POPA ; Restore PSW, INT_MASK, INT_MASK1, & ; WSR registers RET CSEG AT 0FF200CH ; fill in inter ...

  • Intel 80C196NU - page 122

    6-15 STANDARD AND PTS INTERRUPTS 6. At the en d of the ser vice r outine, the POP A i nstruc tio n restores t he origi nal contents of the PSW , INT _MASK, INT _M ASK1, and W SR regis ters; any changes made to these registe rs durin g the interrupt se rvic e routine are overwri tten. Beca use inte r rupt c all s can not occur i mm edia tel y foll o ...

  • Intel 80C196NU - page 123

    8XC1 96NP , 80C196NU USER’S MANUAL 6-16 INT _PE ND Address: Reset Sta te : 0009H 00 H When h ardwar e d etects a pe nding int erru pt, i t set s the corr espo ndin g bit in the in terr upt p endi ng (INT _PE ND or INT _PE ND1) re gisters. W he n the vecto r is take n, the har dware cle ars th e pen ding b it. Softwa re ca n gene rat e an interr u ...

  • Intel 80C196NU - page 124

    6-17 STANDARD AND PTS INTERRUPTS 6.6 INITIALIZING THE P TS CONTRO L BLOCKS Each P T S interrupt requires a block of da ta, in register RAM, called the P TS control block (P TS CB). The P TSC B identi fi es which P T S microcode r outine will be inv o ked and sets up the specifi c parameters for t he r outine. Y ou must s et up the P T SC B for each ...

  • Intel 80C196NU - page 125

    8XC1 96NP , 80C196NU USER’S MANUAL 6-18 The address of the fi rst (lowest ) P TSC B byte is sto red i n the P T S vec tor table in spe cial -pur pose memory (see “Special- purpose Memory” o n page 5-6). Figure 6 -9 shows the P TSCB for e ach P T S mode . U nuse d P T SCB byte s can be use d a s extra RAM . NOTE The P TSC B mus t be l oca te d ...

  • Intel 80C196NU - page 126

    6-19 STANDARD AND PTS INTERRUPTS 6.6.2 S elec ting th e PT S M od e The second b yte of each P T SCB is always an 8-bit value ca lled P TSCON. Bi ts 5–7 select the P T S mode (Figure 6-1 1 ). The function of bits 0–4 dif fe r for each P TS mode . Refer to the s ectio ns that describe eac h mode i n det ail to see the f unctio n of these bit s. ...

  • Intel 80C196NU - page 127

    8XC1 96NP , 80C196NU USER’S MANUAL 6-20 6.6.3 S ingle T ransfer M ode In single transfer mode , an interrupt c ause s the P T S to transfer a si n g le byte or word (selecte d by the BW bit in P TSC ON) from one mem ory location to another . This mode i s typically used with seri al I/ O o r s ync h ronous se rial I/O interrupts. It can a lso be ...

  • Intel 80C196NU - page 128

    6-21 STANDARD AND PTS INTERRUPTS PTS Sin gle T ra nsfer Mo de Cont rol Bloc k In single transfe r m ode , the PTS contro l b lo ck contain s a so urce and desti nati on addres s (P T SSRC and PTS DST), a cont rol registe r (PTSCON) , and a tra nsfe r cou nt (PTSCOUNT). 7 0 Unu sed 0 0 0 0 0 0 0 0 7 0 Unu sed 0 0 0 0 0 0 0 0 15 8 PTSDST (HI) PTS Des ...

  • Intel 80C196NU - page 129

    8XC1 96NP , 80C196NU USER’S MANUAL 6-22 The P TSCB in T a ble 6-5 d efine s nine P TS cycles. Each cycle moves a sin g le word from loca t ion 20H to an e xterna l memory loc ation. T he P TS transfers t he fi rst word to l ocatio n 6000H. Then it increme nts and upd a t es t he dest inat i on ad dress and dec reme nts the P T SC OUNT re gist er; ...

  • Intel 80C196NU - page 130

    6-23 STANDARD AND PTS INTERRUPTS 6.6.4 Block T ransfer Mode In block transfer mode, an interrup t causes t he P TS to move a block of bytes o r words from one memory location to another . See AP-445, 8X C196K R Periphe rals: A User ’ s Point of V iew , f or a p- plicatio n exam ples wi th code. Fig ure 6- 1 3 shows the P TS control block for bloc ...

  • Intel 80C196NU - page 131

    8XC1 96NP , 80C196NU USER’S MANUAL 6-24 PTS Bloc k T ran sfer Mod e Contro l Block In b l ock transfe r mode, t he PTS control b l ock con tains a b lock size (P T SBL OC K), a source and destinati on a ddress (P T SSRC and PTSDST), a c o nt rol r egiste r (PTSCON), and a tran sfer cou nt (P TSCOUNT). 7 0 Unu sed 0 0 0 0 0 0 0 0 7 0 PTSBL OCK PTS ...

  • Intel 80C196NU - page 132

    6-25 STANDARD AND PTS INTERRUPTS Reg iste r Lo catio n Functio n PTSCON PTSCB + 1 PTS Control B its M2:0 PTS Mode The se b its sel ect t he PTS m ode : M2 M1 M0 000b l o c k t r a n s f e r m o d e BW Byte /Word Transfe r 0 = word tra nsfe r 1 = byte tra nsfe r SU Up date PTSSRC 0 = relo ad o rig inal PTS sou r ce add ress a fte r each b loc k t ra ...

  • Intel 80C196NU - page 133

    8XC1 96NP , 80C196NU USER’S MANUAL 6-26 6. 6.5 P W M Mo des The PWM to ggle an d PWM rem ap m odes are desi gned for use with the e vent processor ar ray (EP A) to generate pul se-wi dth modulated (PWM ) output signa ls. These mo des can also be use d with an interrupt s ignal fr om any other sourc e. The P WM toggle mode use s a single EP A c ha ...

  • Intel 80C196NU - page 134

    6-27 STANDARD AND PTS INTERRUPTS Figure 6-14. A Generic PWM Waveform The PW M mo d es d o not use a P TSCOUNT register to specify the number of consecutive P TS cycles. T o s top p roducing the PWM output, first cl e a r the P T SSEL. x bi t to disabl e P TS service for the interrupt and t hen use t he int errupt servi ce routine to rec on figure t ...

  • Intel 80C196NU - page 135

    8XC1 96NP , 80C196NU USER’S MANUAL 6-28 5. Configure P1.0 to s erve as the EP A 0 o utput. — C lear P1_DIR.0 (s elects o utput). — Set P 1_MOD E .0 (se lects the EP A0 specia l-funct ion signal ) . — Set P 1_R EG. 0 (i nitia lizes t he out put t o “ 1”). 6. Se t up E P A0. — Load EP A0_CON with 0078H (timer 1, com pare, to g gle outpu ...

  • Intel 80C196NU - page 136

    6-29 STANDARD AND PTS INTERRUPTS PT S PW M T o ggl e Mo de Cont rol Bl ock In PW M to ggle mod e, the PTS uses a sin gle E P A chan ne l to g ener ate a pulse -wid th mo dula ted (PWM ) outp ut signa l. The contro l blo c k c o nta ins reg iste rs th at cont ai n the PWM on-tim e (PTSCONST 1), the PW M off-ti m e ( PTSCONST2 ), t he ad d ress point ...

  • Intel 80C196NU - page 137

    8XC1 96NP , 80C196NU USER’S MANUAL 6-30 Figure 6- 16 is a flow diagram of the EP A and P TS ope rations for this e xampl e. Operat ion begi ns when the t ime r is enabled (at time = 0 in Figure 6-14 on page 6-27) by the write to T1CO NTR OL. The first t i mer m atch occ u rs at time = T1. T he EP A toggl es the output pin to zero an d genera tes ...

  • Intel 80C196NU - page 138

    6-31 STANDARD AND PTS INTERRUPTS Figure 6-16. EP A and PTS Operat ions for the PWM T oggle Mode Example Y ou can m o d i fy the dut y cyc le without interrupti ng t he PWM operatio n. T o cha nge the dut y cyc le durin g a PWM cycl e, the P TS servi ce routine should writ e new T 1 and T 2 – T1 values to CSTORE1 a nd C STORE 2 a nd sel ect normal ...

  • Intel 80C196NU - page 139

    8XC1 96NP , 80C196NU USER’S MANUAL 6-32 When the next t im er m at ch occurs, t he P TS cyc le (Fi g u re 6- 16) increm ent s E P A 0_T IM E by T 1 (if TBIT is zero (output = 0)) or T2 – T1 (if TBIT is one (output = 1)) . (Note that alth o ugh the value s of the EP A 0 out put and TBI T are t he same in thi s exa mpl e, these tw o value s are u ...

  • Intel 80C196NU - page 140

    6-33 STANDARD AND PTS INTERRUPTS 4. Se t up E P A0 and EP A 1. — Load EP A0_CON with 68H (t ime r 1 , compa re mode, as s ert output pin, re-e nable ). — Load EP A1_CON with 158H ( ti mer 1, compare mode, deas sert output pin, re-enable, remap e nable d ). — Load EP A0_TIM E with 0000H (se lects t ime 0 a s first eve nt t ime fo r EP A0 ). ? ...

  • Intel 80C196NU - page 141

    8XC1 96NP , 80C196NU USER’S MANUAL 6-34 P TS P WM Re map M o de Cont rol Bl oc k In PWM remap mode, the PTS uses two EP A chan nels to genera te a p u lse-wi dth m o du lated (PWM ) out put sig nal. Th e co ntrol bl oc k contai ns re gist ers th at con tain the PW M on-ti me (PTSCONS T1) , the add ress pointer (PTSPTR1), an d a contro l re g iste ...

  • Intel 80C196NU - page 142

    6-35 STANDARD AND PTS INTERRUPTS Figure 6- 18 shows t he E P A and P TS opera tions for thi s exampl e. The first time r ma tch occ urs at ti m e = 0 for EP A0, which asse rts the output and generat es an interrupt. PWM Rem ap Cyc le 1. T he P TS a dds T2 to E P A0 _TIME an d to ggle s t he T BIT . The output rema ins asse rte d unti l the sec o n ...

  • Intel 80C196NU - page 143

    8XC1 96NP , 80C196NU USER’S MANUAL 6-36 Figure 6-18. EP A and PTS Oper ations f or the PW M Remap M o de Example Y ou can cha nge the duty cycle b y chan g ing the t ime that the output is high and keepin g the period constant . Aft er a timer match occurs for EP A1 (when the out p ut falls ) , schedule th e next EP A1 match for T2 + DT , where D ...

  • Intel 80C196NU - page 144

    7 I/O Ports ...

  • Intel 80C196NU - page 145

    ...

  • Intel 80C196NU - page 146

    7- 1 CH A PT ER 7 I/O P O RTS I/O ports pr o vi de a mechanism to transfer in f orma tion betwee n the device and the surrounding system c ircuitry . They can read sys tem status , monitor syste m operat ion, output devi ce status, configure system opti ons, generate contr ol signals, provid e s e ria l communi cation, and so on . Their us efulne s ...

  • Intel 80C196NU - page 147

    7-2 8XC1 96NP , 80C196NU USER’S MANUAL T abl e 7-3 lists the regis ters ass ociated wit h the bidi recti onal ports. Each port has three control reg- ist e rs ( P x _M O DE, P x _DIR , and P x _REG ); the y can be both re ad and writte n. The P x _ PIN regi s- ter is a s ta tus regi ster that ret urns the logi c level prese nt on the pins; i t ca ...

  • Intel 80C196NU - page 148

    7- 3 I/O PORTS 7.2.1 Bid ir ectio nal Po rt O per atio n Figure 7-1 shows t he logic for drivin g the output t ransistors, Q1 an d Q2. O n ports 1, 2, and 3, Q 1 c an so urce at leas t – 3 mA a t V CC – 0.7 vo lt s. On port 4, whic h has a high-cu rrent sink ca pability for the PW Ms, Q1 c an s ou rc e at least –3 m A at 0.45 volts. Q2 can si ...

  • Intel 80C196NU - page 149

    7-4 8XC1 96NP , 80C196NU USER’S MANUAL In special -f unction mo de (sel ected by setting P x _MODE. y ), SFDIR and SFDA T A are i n put to the multiple x ers. T hese signals combine to drive the ga t es o f Q1 a nd Q2 so tha t t he output is hig h , low , o r high impe dance . Spec ial-funct ion output si gnals clear SFDIR; spe cial -func tion i ...

  • Intel 80C196NU - page 150

    7- 5 I/O PORTS Figure 7 -1. Bi directional Port Str ucture Vcc Q2 Q1 Px_REG Px_DIR Sample Latch PH1 Clock Internal Bus SFDATA SFDIR Px_MODE Px_PIN D Q 0 1 0 1 Vcc Vcc Q R S Any Write to Px_MODE Weak Pullup Medium Pullup RESET# RESET# Q3 Q4 Vss Read Port LE 300ns Delay I/O Pin A0238-04 150 Ω to 200 Ω R1 ...

  • Intel 80C196NU - page 151

    7-6 8XC1 96NP , 80C196NU USER’S MANUAL T able 7-4. L ogic T able for Bidirect ional Ports in I/O Mode Con figu rati on Co mpl emen tary Out put Open-d rain Ou tput Inp ut P x _MODE 00 0 0 P x _DIR 00 1 1 SF DIR XX X X SFDA T A XX X X P x _RE G 0 1 0, 1 (N ot e 2 ) 1 Q1 of f on o ff of f Q2 on off on, off (N ote 2 ) o ff P x _PI N 0 1 X (Note 3) h ...

  • Intel 80C196NU - page 152

    7- 7 I/O PORTS 7.2.2 Bid ir ectio nal Po rt Pi n Con fig urati on s Each bidi rec tio nal port pin can be indi vidual ly config ured to operate ei ther a s an I/O pin or as a pin for a spec ia l-function signal . In the spec ial-funct ion configuration, the signal is control led by an on -chip peri pheral or an of f-chi p c ompon e nt. In ei ther c ...

  • Intel 80C196NU - page 153

    7-8 8XC1 96NP , 80C196NU USER’S MANUAL 7.2.3 Bid ir ectio nal Po rt Pi n Con fig urati on Exam p le Assume t hat you wi sh t o confi gure t he pins of a bidirec tional port as s hown in T abl e 7-7. T o d o so, y ou coul d use t he foll owing exa mple code segme nt. T able 7- 8 s h ows the state of each pin after res et and after exec uti on of e ...

  • Intel 80C196NU - page 154

    7- 9 I/O PORTS 7.2.4 Bid ir ectio nal Po rt Co ns id erati ons This sect ion outlines spec ia l considera tions for using the pins of the se ports. Port 1 After reset, your s oftware must con figure the device to match the external system. Thi s is accomplishe d by writing appropriate config- uration data into P1_MO DE. Wr iting to P1_M ODE not onl ...

  • Intel 80C196NU - page 155

    7-10 8XC1 96NP , 80C196NU USER’S MANUAL P2.7/CL KOUT Following rese t , P 2.7 carri es the st r ongly drive n CLKOU T signal. It is no t he ld high. W hen P2.7 i s configured a s CLKOUT , i t is always a complem ent ary output. P2.7 A value written t o P2_REG. 7 i s held in a buff er until P2_MODE. 7 is cleared, at whi ch time the va lue is l oad ...

  • Intel 80C196NU - page 156

    7-11 I/O PORTS 7.2.5 Desi gn Consider atio ns for E xtern al Interrupt In pu ts T o c onfigure a po rt pin tha t serves a s a n external i nte rr upt in put, you m ust set t he corresponding bits in the co nfig uratio n regist ers (P x _DIR, P x _M ODE, and P x _REG). However , set ti ng th e P x _MODE bit cause s the devic e to set the correspondi ...

  • Intel 80C196NU - page 157

    7-12 8XC1 96NP , 80C196NU USER’S MANUAL 7.3.1 E PO RT Op erati on As Figure 7-2 shows, each EPOR T pin serves either as I/O or a s an address l ine, a s selected by the I/O mult iplexer . This multipl exer is co ntrolled by the EP_M ODE regi ster . If EP_MODE . x is clear (I/O mode), the pin ser ves a s I/O until E P_M OD E. x is cha ng e d . T a ...

  • Intel 80C196NU - page 158

    7-13 I/O PORTS Figure 7-2. EPORT Bl oc k Diagram If EP_MO DE . x is set (address mode), the address multiple xer det ermi nes the address source . For an inst ruc tion fet ch, the a ddre ss m ult ipl exe r is set to the CODE i np ut, which se lects t he e xten ded program counter (EPC) as the address source . For a data fet ch, o r when there is no ...

  • Intel 80C196NU - page 159

    7-14 8XC1 96NP , 80C196NU USER’S MANUAL The 8XC196NP allows you to cha nge the value o f E P_R EG to control whi ch memory page a n on- extended i nstruc tion accesses . Howeve r , soft ware tool s require tha t EP_R EG be equal to 00H. The 80C196NU forces all nonexten d ed data accesses to page 00H. Y ou cannot use EP_RE G to change page s. Y ou ...

  • Intel 80C196NU - page 160

    7-15 I/O PORTS Figure 7-3. EPORT Structure Vcc Q2 Q1 EP_REG EP_MODE Sample Latch PH1 Clock Internal Bus EP_PIN D Q 0 1 Vcc Vcc Weak Pullup Medium Pullup RESET# Q3 Q4 Buffer Vss Read Port LE 300ns Delay I/O Pin Address Bit from Address MUX EP_DIR POWERDOWN# IDLE# HOLD# RESET# DATA A0241-02 R1 150 Ω to 200 Ω ...

  • Intel 80C196NU - page 161

    7-16 8XC1 96NP , 80C196NU USER’S MANUAL 7.3.1.5 Input Mode Input mode is obta ined by c onfiguring the pin as an o pen-drain output (EP_DIR set and EP_MO DE clear) and writ ing a one to EP_R EG . x . In this configurat ion, Q1 and Q2 a re both off , allowi n g an ext ernal device to dri ve the pin. T o dete rmi ne the val ue of t he I/O pin, read ...

  • Intel 80C196NU - page 162

    7-17 I/O PORTS 7.3 .2 Con fig uri ng E PO RT P i ns Each EP OR T pi n can be indivi dually configured t o o perate either a s an exte nde d-ad dress signal or as an I/O pin i n one of these modes: • complem ent ary output (output o nly) • high-impedanc e i nput or open-drain output (input, output, or bidi rec tio nal) 7.3.2.1 Configuring EPORT ...

  • Intel 80C196NU - page 163

    7-18 8XC1 96NP , 80C196NU USER’S MANUAL 7.3.3 E PO RT Con sid erati on s This sect ion outlines consi derat i ons for using t he EPOR T pin s. 7.3.3.1 EPORT Status Duri ng Reset, CCB Fet ch, I dle, Power down, and Hol d During reset, the EPOR T pins are forced t o their e xtended -address fu nct i ons a nd are weakly pulle d hig h . During the CC ...

  • Intel 80C196NU - page 164

    7-19 I/O PORTS 3. An y n onexte nde d or dire ct ins truct i on that a cc ess es the regi ster fi le or the wi n d owable SFRs is a lways directe d internal ly to these area s , regar d l ess of the page from whic h c o de is exec uti n g. This effect ive ly ma ps the registe r fi le and wi n dowa ble SFRs into every page. Extended inst ruct ions c ...

  • Intel 80C196NU - page 165

    ...

  • Intel 80C196NU - page 166

    8 Serial I/O (SIO) Po rt ...

  • Intel 80C196NU - page 167

    ...

  • Intel 80C196NU - page 168

    8- 1 CH A PT ER 8 SE RIAL I/O (S IO) PO RT A serial input/ output (SIO) port provides a m e a ns for th e syst em to comm u nica t e wi th ext ernal devices . This devic e has a seria l I/O (SIO) port that shares pins with p ort 2. This cha pte r desc ribes the SIO port and e xplai ns how t o configure it. Chapte r 7, “ I/O Po rts,” expla ins h ...

  • Intel 80C196NU - page 169

    8-2 8XC1 96NP , 80C196NU USER’S MANUAL An i ndependent , 15-bit baud-rat e genera tor c ontrols t he ba ud r ate of the seri al port. E ither the in - ternal periphera l cloc k or T1C LK can provid e the c lock signal. The baud-rate register (SP_BAUD) se lects the clock s ource and t he baud rat e. 8.2 SE RIAL I / O PORT SIG NALS AND REG ISTERS T ...

  • Intel 80C196NU - page 170

    8- 3 SERIAL I/O (SI O) PORT P1_PIN 1FD6 H Po rt 1 Pin State If you are u sin g T1CL K (P 1.4) a s the clo ck so urce for th e b au d- rate gen era tor, you can re ad P1 _P IN.4 to d eterm in e t he curre nt valu e of T 1CL K. P1_R EG 1 FD4 H Po rt 1 Ou tp ut Dat a T o u se T1 CL K a s the clo ck sou rce f or the b aud-ra te g enera tor , set P1_ RE ...

  • Intel 80C196NU - page 171

    8-4 8XC1 96NP , 80C196NU USER’S MANUAL 8.3 SE RIAL PO RT MO DE S The serial p or t has bot h synchronous and asynchr o nous operatin g modes for transmi ssio n and re- ception. T his sec tion des cribe s the operat ion of e ac h m ode. 8.3.1 S ynch ron ous M o de (Mo de 0) The most c ommon use of m o de 0, the sync h ronou s mode , is to exp and ...

  • Intel 80C196NU - page 172

    8- 5 SERIAL I/O (SI O) PORT In mode 0, RXD must be enabl ed f or recept ions and disable d for transmis sions. (See “Pr ogram- min g the Cont r ol Regi ster” on pa ge 8-8 .) W hen R XD is e nable d, eit her a ris ing e dge o n the RX D input or clearing the re ceive inter r upt (RI) flag in SP_ST A TUS st art s a recept ion. When RXD i s disabl ...

  • Intel 80C196NU - page 173

    8-6 8XC1 96NP , 80C196NU USER’S MANUAL When the s eria l p ort is configured for mode 1, 2, or 3, writing t o SBUF_TX c ause s the s eria l p ort to start transm itting dat a. New dat a pla ce d in S BUF_T X is transm itted only a fter the stop bit of the p revious da ta has be en se nt. A fal lin g edge on the RX D input ca uses t he s eria l po ...

  • Intel 80C196NU - page 174

    8- 7 SERIAL I/O (SI O) PORT 8.3.2.2 Mode 2 Mo de 2 is the a synchrono us , ninth -bit recognition m ode. This mode is comm only used with m ode 3 for mul tip rocessor comm unications. Figure 8-5 shows t he da ta frame used in t his mode. It con - sists of a st art bit (0), ni ne dat a bi ts (LSB fi rst), and a stop bit (1). Duri ng t ransm issions, ...

  • Intel 80C196NU - page 175

    8-8 8XC1 96NP , 80C196NU USER’S MANUAL 8.3.2.5 Multipr ocessor Co m municatio ns Mo des 2 an d 3 are provi ded fo r mul t ip ro c essor communicatio n s . In mode 2, the seri a l p ort s e ts the RI i nterrupt pending bit only when the ninth data bit i s set. In m ode 3, the seria l p ort sets the RI interrupt pe n ding bit regardless of the valu ...

  • Intel 80C196NU - page 176

    8- 9 SERIAL I/O (SI O) PORT SP_CON Address : Re set State: 1 FBBH 00H The se rial p ort control (SP_ CON) reg iste r sel ects th e com m unicat io ns m od e and en able s or d isab le s the recei ver, parity chec king , a nd nine-b it data tra nsmi s sion . F or t he 80C1 96NU, i t a lso en ab les o r disab le s the divid e-b y- two pre sca le r . ...

  • Intel 80C196NU - page 177

    8-10 8XC1 96NP , 80C196NU USER’S MANUAL 1:0 M 1 :0 Mo de Se le ctio n These b it s sele ct th e co mmu ni catio ns m o de. M1 M0 00 m o d e 0 01 m o d e 1 10 m o d e 2 11 m o d e 3 SP _CON (Co nti nue d) Address: Re set State: 1 FBBH 00H The se rial p ort control (SP_ CON) reg iste r sel ects th e com m unicat io ns m od e and en able s or d isab ...

  • Intel 80C196NU - page 178

    8-11 SERIAL I/O (SI O) PORT SP_ BAU D Address: Reset Sta te : 1F BCH 000 0 H The seria l p ort b au d rate (SP _BA UD) re gi ster se lects t he seri al po rt b aud rat e a n d clo c k source. Th e most-sig ni fica nt bit sel ects th e clo ck sour ce. The l owe r 15 bi ts rep resen t BAUD _V A LUE, an un sign ed inte ger th at de te rmine s th e bau ...

  • Intel 80C196NU - page 179

    8-12 8XC1 96NP , 80C196NU USER’S MANUAL CAUT ION For mo d e 0 receptions, the BAUD_V ALUE must be 0002H or grea ter . Othe rwis e, the re sulting da ta in t he re ce ive shi ft re gist e r will be inc orre ct. The reason for this restric t ion is t hat t he rece ive shift register is clocke d from an internal signal rathe r than t he signal on TX ...

  • Intel 80C196NU - page 180

    8-13 SERIAL I/O (SI O) PORT 8.4.4 Enab ling the S eri al P or t I nterr upts The seria l port ha s both a t ransm it inter rupt (TI) and a receive inte rrupt ( R I). T o e nabl e an inter- ru pt, set th e co rr espon ding m ask bi t in the inte rrupt mas k regist er (see T able 8-2 on page 8-2 ) an d execute the EI instruct ion to glo b ally enabl ...

  • Intel 80C196NU - page 181

    8-14 8XC1 96NP , 80C196NU USER’S MANUAL The rece ive r checks f or a valid st o p bit. Unless a stop bit is f ound w i thin the appropr ia te time, th e framin g e rr or (FE) bit in the SP_ST A TUS regist er is se t . Whe n t he s t op bit is det e c ted, the da t a in the re ceive shift regi ster i s loa ded into SB UF_R X a n d the rec eive int ...

  • Intel 80C196NU - page 182

    8-15 SERIAL I/O (SI O) PORT The rece iv e interrupt (RI) flag i n di cates whether a n incomi ng d a t a byte h a s been received. The transmi t in t errupt (TI) fla g indicates whether a dat a byte has finis hed transmitting. Thes e flags a lso s et t he c orr e spond ing bit s i n the inte r rupt pen ding re gist er . A rec epti on or t ransmi ss ...

  • Intel 80C196NU - page 183

    ...

  • Intel 80C196NU - page 184

    9 Pulse-width Modulator ...

  • Intel 80C196NU - page 185

    ...

  • Intel 80C196NU - page 186

    9- 1 CH A PT ER 9 PUL SE -W IDT H MO DUL AT O R The pulse-wi dth modula tor (PWM ) m odule has three outp ut pins, each of w h ich c an output a PWM s ignal with a fixed freque ncy a nd a variabl e du ty cyc le. Thes e outputs c an be used to drive motors that require an unfiltered PWM waveform for opt imal ef ficienc y , or they can be f il t e r ...

  • Intel 80C196NU - page 187

    9-2 8XC1 96NP , 80C196NU USER’S MANUAL Figure 9 - 2. PWM Block Diagr am (8 0 C196NU Onl y) 9.2 PWM SIGNAL S AND RE GIS TE RS T abl e 9-1 describes the PW M ’ s signal s a n d T abl e 9 -2 briefly des cri bes t he control a nd sta tus reg- ist e rs . T abl e 9-1. PW M Si gnals Port P in PW M Sig nal PWM Si gna l T yp e Desc ripti on P4.0 PWM 0 O ...

  • Intel 80C196NU - page 188

    9- 3 PULSE-WIDTH M ODULATOR 9.3 PWM OP E RATI ON For the 8XC196NP , CON _REG0.0 (CLK0) control s the PWM output frequenc y by e nabling or disabli n g the divide -by-two clock presc aler . Enabli ng the presc aler c auses t he 8-bit counte r to in - crement once every two st ate times; disabli ng it c ause s the counter t o incre ment once eve ry s ...

  • Intel 80C196NU - page 189

    9-4 8XC1 96NP , 80C196NU USER’S MANUAL For the 80C196NU, two bits control the PW M output fre quency , CON_REG0. 0 (CLK0) and CON _REG0.1 (CL K 1 ). The two bits control the PWM output frequency by enabling o r disabl ing the divi de-by-two or di vide - by-four clock prescaler . Each control regist er (PWM x _CONTROL; x = 0, 1, or 2) c ontr ols t ...

  • Intel 80C196NU - page 190

    9- 5 PULSE-WIDTH M ODULATOR Figure 9-3. PWM Out p ut W a v eform s 9.4 PROG RAM MING TH E F REQ UENC Y AND P E RIOD The PWM m odule provides two s electable , fixed PWM outp ut frequencies for a specified internal operat ing frequenc y (f). T able 9 -3 shows the PWM out put frequenci es for com mon operat ing freque nci es on the 8XC1 96NP . The va ...

  • Intel 80C196NU - page 191

    9-6 8XC1 96NP , 80C196NU USER’S MANUAL For the 80C196NU, the PWM module provides three selectable , fixed PWM output frequencies for a spec ified inte rnal operating freq uency (f). T able 9-3 shows the PW M output frequenc ies for commo n operating frequenci es. The v alue of bits 0 an d 1 in the CON_R EG0 re gist er determ ine s the out put fre ...

  • Intel 80C196NU - page 192

    9- 7 PULSE-WIDTH M ODULATOR 9.5 PROG RAM MING TH E DUTY CYCLE The valu e written to the PWM x _CONTR O L regist er cont rols the width of the high pulse, effec- tivel y contr o l ling the d u ty cyc le. The 8-bit va lue writ ten to t he control register is loaded i n to a buffer , and thi s value is used during the next perio d . Use t he following ...

  • Intel 80C196NU - page 193

    9-8 8XC1 96NP , 80C196NU USER’S MANUAL Pulsewid th (i n µ s) = D u ty Cy cl e (in %) = where: PWM x _CON = 8-bit v a lue to l o ad i n to the PWM x _CONTROL re gister Pulsewid th = wid th of e a ch high pu lse f = op era ti ng fr e qu en c y , in M Hz T PWM = out put p er i od on t he PW M pi n , i n µ s † 80 C 19 6NU only . Cl ock P res ca l ...

  • Intel 80C196NU - page 194

    9- 9 PULSE-WIDTH M ODULATOR 9.5 .1 S am pl e C alcu la ti on s For example , assum e that the o pe rating frequenc y equal s 25 MH z, the desired p eriod o f the P W M output wa veform i s either 20.4 8 µs (5 12 state ti mes) if the divide-by-two presc aler is di sabled or 40.96 µs (1,024 s tate times) if the presc aler is enabled . If PWM x _CON ...

  • Intel 80C196NU - page 195

    9-10 8XC1 96NP , 80C196NU USER’S MANUAL Figure 9-6. D/A Buff er Block Diagram Figure 9-7 shows a sample circui t used fo r low output current s (less t han 10 0 µ A). Co nsider t em- perature and p ower -supp ly drift when selec ting com ponents for the ex t ernal D/A c irc uit ry . Wi t h prope r components, a highly accurate 8- bit D/A convert ...

  • Intel 80C196NU - page 196

    10 Event Pr ocessor Array (EP A) ...

  • Intel 80C196NU - page 197

    ...

  • Intel 80C196NU - page 198

    10 -1 CHAPTER 10 EVENT P ROCES SOR ARRAY (E P A ) Contr ol applications ofte n req uire high-speed eve nt control. For exa mple, the cont roller may nee d to periodic ally genera te p ulse-widt h modula ted outputs or an inte rrupt. In anot her applicat ion, the controlle r may monit or an inp u t s ignal to determi ne the s t atus of an ext ernal ...

  • Intel 80C196NU - page 199

    8XC1 96NP , 80C196NU USER’S MANUAL 10 -2 Figure 10-1. EP A Blo ck Diagram 10.2 EP A AND TIM E R/ COUNTE R S IGNAL S AND REGISTERS T abl e 10-1 describe s the EP A and time r/c ounter input and o utput signa ls. Each signal is multi- plexed wi th a port pin a s shown i n the first column. T abl e 10-2 briefl y desc ribe s the regi sters for the EP ...

  • Intel 80C196NU - page 200

    10 -3 EVENT PROCESSOR ARRAY (EP A) T a ble 10-2. EP A Cont rol and Stat us Register s Mne m oni c Add res s Desc riptio n EP A_M ASK 1F 9C H EP A Mas k Four bits (OVR0, OVR1, OVR2, an d OVR3) in th i s 8-bit registe r enab le an d disab le (m as k) the individ ua l captu re o ve rru n inte rrup t sour ces associate d with cap ture /com p are cha nn ...

  • Intel 80C196NU - page 201

    8XC1 96NP , 80C196NU USER’S MANUAL 10 -4 P 1_MODE 1 FD0H Port 1 Mo de Each bit of P1 _M ODE controls wheth er the correspo nding pin functi on s as a standa rd I/O port pin or as a speci al-fun ctio n sign al. S ett in g a b it co nfig ure s a p in a s a sp ecia l-fu ncti on sig nal; clea ri ng a b i t configur es a pin a s a s tan da rd I/O port ...

  • Intel 80C196NU - page 202

    10 -5 EVENT PROCESSOR ARRAY (EP A) 10.3 TIMER/C OUNTER FUNCTIONAL OV ERV IEW The EP A has tw o 1 6 -bi t up/down timer/counters, timer 1 an d tim e r 2, whi ch c an be c locked in- ter nally o r exte rnal ly . E ach is calle d a time r i f it is cloc ke d int ernal ly a n d a counter if it i s clo cked external ly . Fig ure 10- 2 i llus tra tes t h ...

  • Intel 80C196NU - page 203

    8XC1 96NP , 80C196NU USER’S MANUAL 10 -6 The timer/ counters can be used as time bases for input capture s, output compares , and p ro- grammed i nterrupts (sof t ware tim ers). W hen a cou n t er increme nts from FFFEH to FFFFH or dec - rements from 0001H to 0000H, the co u nter-overflow inte rrupt pending b it is s et. This b it can optionally ...

  • Intel 80C196NU - page 204

    10 -7 EVENT PROCESSOR ARRAY (EP A) Figure 1 0-3. Quadrat ure Mode I nter face T abl e 10-3. Quadrature Mode T ruth T a ble Sta te o f X_i nte rnal (T x CLK) S tate of Y_ inte rna l (T x DIR) Co unt Direc tio n ↑ 0 Increm en t ↓ 1 Increm en t 0 ↓ Increm en t 1 ↑ Increm en t ↓ 0 D ec reme nt ↑ 1 D ec reme nt 0 ↑ De crem ent 1 ↓ De cre ...

  • Intel 80C196NU - page 205

    8XC1 96NP , 80C196NU USER’S MANUAL 10 -8 Fi gur e 10 -4. Quadr ature Mode T im ing and Count 10.4 EP A CHANNEL FUNCTIONAL OV E RV IEW The EP A has f o ur prog ramm able c apture /compare channe ls that can perform t he foll owing tasks. • capture the current t i mer val ue when a specified trans ition occurs on t he EP A pin • clear, set , or ...

  • Intel 80C196NU - page 206

    10 -9 EVENT PROCESSOR ARRAY (EP A) Figure 1 0-5. A Sin gle EP A Capt ure/Compar e Channel 10.4.1 Op erati ng in Capture Mo de In capture m ode, when a valid event occurs on the pi n, the value of the sel e cted ti me r is captu red into a buffer . The timer val ue is then trans ferred from the buffer to the EP A x _TIM E re gist er , which set s th ...

  • Intel 80C196NU - page 207

    8XC1 96NP , 80C196NU USER’S MANUAL 10 -10 Fig ure 10-6. EP A Simpl ified Input -capture Str ucture If a third event occ urs bef ore the CPU reads the event -time registe r , the ove rwrite bit (EP A x _CON. 0) determines how the EP A will handle the event. If the bi t is c le ar , the EP A ig nore s the thir d event. If the bit is set, the third ...

  • Intel 80C196NU - page 208

    10-11 EVENT PROCESSOR ARRAY (EP A) An input c apture e vent does n o t s et the interrupt pen ding bit until the captured time va lue ac tua lly moves from the capture bu f fer into the EP A x _T IME re gist er . I f t he b u ffer cont ai ns d a ta a n d the P T S is use d to se rvice the interrupts , then two P T S inter rupts occur almost bac k-t ...

  • Intel 80C196NU - page 209

    8XC1 96NP , 80C196NU USER’S MANUAL 10 -12 10.4.1.2 Preventing EP A Overru ns An y one of the following methods can be used t o prevent or recover from an EP A ove r run si tua - t ion. • Cle ar E P A x _CON.0 Wh en t h e o verw ri te bit (E P A x _C ON.0) is zero, the EP A does not consider the captured e dge un til t he EP A x _ T IME re gist ...

  • Intel 80C196NU - page 210

    10-13 EVENT PROCESSOR ARRAY (EP A) The ma ximum output freq uency depends u pon the total interrupt latency and the interrupt-service executi on tim es used b y your system. As additional EP A cha n nels and the other functions o f the microcont roller a re used, the m axi mum PWM frequency decre ases beca use the tota l i nterrupt la - tency an d ...

  • Intel 80C196NU - page 211

    8XC1 96NP , 80C196NU USER’S MANUAL 10 -14 The maxi mum out p ut frequency depends u pon the tota l inter rupt latency a nd inter rupt-servi ce ex- ecution tim e. As additional EP A c hannel s and the othe r functions of the mic roco n troll er are use d, the maxi mum PWM frequenc y decrease s because the total interrupt latenc y and interrupt-se ...

  • Intel 80C196NU - page 212

    10-15 EVENT PROCESSOR ARRAY (EP A) 10.4.2.4 Gene rating the Highest-speed PWM Output Y ou can generat e a highes t-speed, puls e-wi dth modula ted outp ut with a pair of EP A cha n nels and a dedicated time r/c o u nt er . The first chan nel tog gles the out put when the t imer val ue m atche s EP A x _T IM E, an d at some late r time, the se cond ...

  • Intel 80C196NU - page 213

    8XC1 96NP , 80C196NU USER’S MANUAL 10 -16 T1CONTROL Address: Reset Sta te : 1F 90 H 00 H The t imer 1 con trol (T1 CONTROL ) registe r d eterm ines th e clock sou rce, c oun ting dire ctio n, an d count ra te for tim e r 1 . 7 0 CE UD M2 M1 M0 P2 P1 P0 Bit Num ber Bit Mne m oni c F unc tio n 7 CE C ou nter Ena bl e Thi s bit ena bles or di sabl e ...

  • Intel 80C196NU - page 214

    10-17 EVENT PROCESSOR ARRAY (EP A) T2CONTROL Address: Reset Sta te : 1F 94 H 00 H The t imer 2 con trol (T2 CONTROL ) registe r d eterm ines th e clock sou rce, c oun ting dire ctio n, an d count ra te for tim e r 2 . 7 0 CE UD M2 M1 M0 P2 P1 P0 Bit Num ber Bit Mne m oni c F unc tio n 7 CE C ou nter Ena bl e Thi s bit ena bles or di sabl es t he ti ...

  • Intel 80C196NU - page 215

    8XC1 96NP , 80C196NU USER’S MANUAL 10 -18 10.5.3 Prog ram m ing the Capture/ C o mpare Ch ann els The EP A x _C ON regi ster control s the funct ion of its assigned ca pture /com pare channel . The reg- isters for EP A0 an d EP A 2 are i dent ical. The registers for EP A1 and EP A3 have an additional bit, the rem ap bit (RM ), which is use d t o ...

  • Intel 80C196NU - page 216

    10-19 EVENT PROCESSOR ARRAY (EP A) EP A x _CON x = 0– 3 Address: Reset Sta te : T a ble 10- 2 on page 1 0- 3 00H The EP A con trol (EP A x _CON) registe r s cont rol the f un ctio ns o f thei r a ssigne d capture /com p are cha nnels. Th e registe rs for EP A 0 a ndEP A2 are iden tical. Th e re gisters f or E P A1 a nd EP A 3 h ave an add iti ona ...

  • Intel 80C196NU - page 217

    8XC1 96NP , 80C196NU USER’S MANUAL 10 -20 5: 4 M1: 0 EP A Mode S e lec t In ca pt ure m ode, sp ecif ie s the type of eve nt t ha t tr igg er s an inp ut cap ture . In compa re mode, specif ie s the action tha t the EP A execu tes when the re fere nce ti mer m at ch es t he eve nt tim e . M1 M 0 Cap ture M ode E vent 00n o c a p t u r e 0 1 cap t ...

  • Intel 80C196NU - page 218

    10-21 EVENT PROCESSOR ARRAY (EP A) 1 ROT Rese t Op posi te Ti mer Con tro ls d iffer en t fu ncti on s fo r cap ture a nd com p are mod e s. In Cap ture M ode : 0 = ca uses no actio n 1 = re sets the opposite timer In Com pa re M o de: Sele cts the timer t ha t is t o be rese t if the RT bit is set . 0 = se lects t he re fere nce ti mer fo r p ossi ...

  • Intel 80C196NU - page 219

    8XC1 96NP , 80C196NU USER’S MANUAL 10 -22 10.6 ENABL ING T HE EP A INTERRUP TS The EP A genera tes four indivi dual e vent interrupts, EP A3:0, from the four capture/ compare chan - nels and two t i me r in te rrupts, OVR TM1 an d OVR TM2, from timer 1 a nd t ime r 2. These in ter- rupts are dire ctly ma pped into the two 8- b it interrupt pendi ...

  • Intel 80C196NU - page 220

    10-23 EVENT PROCESSOR ARRAY (EP A) The E P A i nte rr upt pe n ding re gist er , EP A_PEN D, has the same bit struc ture as the EP A _ MA SK registe r . E P A_PEND is simi lar to an int errupt pending register i n that it shows the s t a tus of the individual capture/compare overrun i nterrupts. The bi ts in EP A_PEND c an be polled to d e ter- min ...

  • Intel 80C196NU - page 221

    8XC196N P , 80C1 96NU USER ’S MA NUAL 10-2 4 10.8 PRO G RAM MI NG EX AMP L ES FO R E P A CH ANN ELS The t hree p rogram mi ng e xampl es pr ovided in th is s ecti o n de monst ra te the use o f the EP A c hannel for a compare event , for a c apt ure event, and for generat i on of a PWM s igna l. T he progr am s de m- ons trate the de tection of e ...

  • Intel 80C196NU - page 222

    10-25 EVENT PROCESSOR ARRAY (EP A) void poll_epa0() { if(checkbit(int_pend, EPA0_INT_BIT)) { /* Insert user code f or event channel 0 here. */ /* Since this event is absolute and re-enab led, no polling is neccessary.*/ clrbit(int_pend, EPA0_ INT_BIT); } } void main(void) { /* Initialize the time rs before using the epa */ init_timer1(); init_epa0( ...

  • Intel 80C196NU - page 223

    8XC1 96NP , 80C196NU USER’S MANUAL 10 -26 time_value = epa0_tim e; /* must read to prevent overrun * / } void init_timer1() { t1control = COUNT_ENABLE ¦ COUNT_UP ¦ CLOCK_INTERNAL ¦ DIVIDE_BY_1; } void main(void) { unsigned int time_val ue; /* Initialize the tim ers and interrupts before using the EPA */ init_timer1(); init_epa0(); enable(); /* ...

  • Intel 80C196NU - page 224

    10-27 EVENT PROCESSOR ARRAY (EP A) void Init_PWM_toggle_P TS3(void) { disable(); /* disable all interrupts */ disable_pts(); /* disable the PTS interrupts */ PWM_toggle_CB_3.co nstant2 = 127; PWM_toggle_CB_3.co nstant1 = 127; PWM_toggle_CB_3.pt s_ptr = (void *)&EPA0_TIME; PWM_toggle_CB_3.pt scon = 0x42; /* Sample code that co uld be used to gen ...

  • Intel 80C196NU - page 225

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  • Intel 80C196NU - page 226

    11 Minimum H ardwar e Considerat ions ...

  • Intel 80C196NU - page 227

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  • Intel 80C196NU - page 228

    11 -1 C HAPT ER 1 1 MINIM UM HARDWARE CONSIDE RAT IONS The 8XC196NP and 80C196NU have several basi c req uirements for operation within a syste m. This chapt er describe s options for providing the basic requirement s and discusses other hardware considerat ions. 1 1.1 MINI MUM CON NECT IONS T abl e 1 1-1 list s t he signal s t hat are required fo ...

  • Intel 80C196NU - page 229

    8XC1 96NP , 80C196NU USER’S MANUAL 11 -2 1 1. 1.1 Unused I npu ts For predic tabl e performanc e , it i s i mportant to tie unused inp u t s to V CC or V SS . Ot herwise, they can floa t to a mi d- voltage level and draw exc essi ve current . Unused interrupt inputs may generate spur ious i nte r rupts if left unconnec ted. 1 1. 1. 2 I / O Port P ...

  • Intel 80C196NU - page 230

    11 -3 MINIMUM HARDWARE CONSIDERATI ON S Figure 1 1 - 1. Minimum Hardwar e Co nnections ALE INST XTAL1 XTAL2 V CC (Note 2) 0.01 µF NMI READY V CC Bus Control (Note 4) 20 pF 20 pF (Note 1) 4.7 µF + .22 µF RESET# BHE# WR# RD# EA# V CC A2415-02 V SS RPD 8XC196 Device V CC Notes:  1. See the datasheet for the oscillator frequency range (F OS ...

  • Intel 80C196NU - page 231

    8XC1 96NP , 80C196NU USER’S MANUAL 11 -4 1 1.2 AP PLYING AND REMOVING POWER When power is first applied to the device, RESE T# must remai n contin uously low for a t least one state ti me aft er the p ower supply is wit hin tole ranc e an d the oscilla tor/ clock ha s stabi lized; oth - erwise, operat ion m ight be u npredictable . Similarly , wh ...

  • Intel 80C196NU - page 232

    11 -5 MINIMUM HARDWARE CONSIDERATI ON S Multilaye r print ed circ uit boards wi th sepa rate V CC and grou nd pla nes a lso h e l p to m ini mize noise. For more informat ion on noise p rotection, re fer to AP-125, De signing Micr ocontro ll er Sys- tems f or N oisy Envi r onme nts and AP-7 11 , EMI Des ign T ec hniq u es f or Mic r ocontro ller s ...

  • Intel 80C196NU - page 233

    8XC1 96NP , 80C196NU USER’S MANUAL 11 -6 Figure 1 1-4 shows the c onnections betwe en the external crystal and th e device. Whe n designing an external osc i ll a to r circuit, conside r t h e ef fec ts of parasit i c board capac i t ance, extended op er- ating tempe ratu res, and crystal spec i fi catio ns. Consult the manufacture r’ s d atash ...

  • Intel 80C196NU - page 234

    11 -7 MINIMUM HARDWARE CONSIDERATI ON S 1 1.5 USI NG AN EX TERNAL CLOCK SOURCE T o use an exte rnal clock sourc e, apply a c lock si gnal to XT AL1 and l et XT AL2 float (Fig u re 1 1 -5). T o ensure pr o per ope ration, t he external clock source must m e e t the minim um high an d low ti mes (T XH XX and T XLX X ) and the m axi mum ri se and fal ...

  • Intel 80C196NU - page 235

    8XC1 96NP , 80C196NU USER’S MANUAL 11 -8 1 1. 6 RE S E TT ING T HE DE V ICE Res et f o rces the device in to a known state . As soon as RESET# is asserted, the I/O pins, the con - trol pins, a nd the regis ters are drive n to the ir rese t state s. (T a ble B-5 on page B- 13 lists the re set states of the pins. See T a ble C-2 on page C-2 for the ...

  • Intel 80C196NU - page 236

    11 -9 MINIMUM HARDWARE CONSIDERATI ON S The following e vents will reset t he de vice (see Figu re 1 1- 8) : • an external device pulls the R ESE T# pin low • the CPU issues the rese t (RST) i nstructi on • the CPU issue s an idle/powerdown (IDLPD ) instruct ion w ith an illegal key o perand The following paragraphs de scribe ea ch of t hese ...

  • Intel 80C196NU - page 237

    8XC1 96NP , 80C196NU USER’S MANUAL 11 -10 The si mples t wa y t o reset the devic e is to inse rt a capa ci tor bet ween the R E S ET # pin an d V SS , a s shown in Fig ure 1 1-9. The devi ce has a n interna l p ull-up resistor ( R RST ) s hown in Figure 1 1-8. RESE T# should remain assert ed for at lea st one state t i me after V CC and X T AL1 ...

  • Intel 80C196NU - page 238

    11-11 MINIMUM HARDWARE CONSIDERATI ON S 1 1. 6. 2 Issuing the Res et (RS T) Instruc tion The RST inst ruct ion (o pcode FFH) resets t he devi ce by pulli ng RES ET# lo w f or 16 state times. It a l so clears the processor status word ( P SW), s e ts the extended and master pr o gram counte rs (EPC /PC) to FF2 08 0H, and r ese ts the spe c i a l fun ...

  • Intel 80C196NU - page 239

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  • Intel 80C196NU - page 240

    12 Special Op erating Modes ...

  • Intel 80C196NU - page 241

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  • Intel 80C196NU - page 242

    12 -1 CHAPTER 12 SPE CIA L OPE RATI NG M ODES The 8XC 196NP and 80C 196NU provide the fol lowi ng p ower saving m odes: idle, st andby (80C196NU only), and powerdown. They also prov ide an on-ci rcuit emulatio n (ONCE) m ode that electri cally isolates the device from the other system components. This cha pte r describe s each mode a n d explai ns ...

  • Intel 80C196NU - page 243

    12 -2 8XC1 96NP , 80C196NU USER’S MANUAL — PLL EN2 : 1 (80 C19 6NU on ly ) I Ph ase Lock Loo p 1 a n d 2 Enable T hes e i np ut pins a r e used to ena ble t he on- ch ip cl ock mu lt i plie r feature a nd select e ither the d oubl ed o r qua drupl ed clock spe ed. CAUTION: If PL LEN1 i s held l ow whi le PLLEN2 is held h ig h, th e device will ...

  • Intel 80C196NU - page 244

    12 -3 SPECIAL OPERATING MODES 12.2 REDUCI NG POWE R CONS UM P TION Each power -saving mode conser ves power by disabling portions of the i nternal cloc k circui tr y (Figure 12-1 an d Fig ure 12-2). The fol lowi n g paragraphs desc ribe each mo de in detail. I NT_ MA SK1 001 3H In ter rup t M a sk 1 Bi t s 5 an d 6 o f th i s r e gi st er en ab le ...

  • Intel 80C196NU - page 245

    12 -4 8XC1 96NP , 80C196NU USER’S MANUAL Figure 12-1. Cl o ck Control During Power -saving Modes (8XC196NP) A3161-01 Clock Generators CPU Clocks (PH1, PH2) Divide-by-two Circuit Peripheral Clocks (PH1, PH2) CLKOUT Disable Clocks (Powerdown) Disable Clocks (Idle, Powerdown) XTAL1 XTAL2 Disable Oscillator (Powerdown) Disable Clock ...

  • Intel 80C196NU - page 246

    12 -5 SPECIAL OPERATING MODES Figure 12-2. Cl o ck Control During Power-saving Modes (8 0C196NU) 12.3 IDLE MO D E In idle m o de , the devic e’ s power consumption d ecrease s to approximat e ly 40% o f n ormal con- sumption. Inte rnal logic holds the CPU clocks a t logi c z ero, ca u s ing the C PU to stop execut ing instruct ions. Neithe r the ...

  • Intel 80C196NU - page 247

    12 -6 8XC1 96NP , 80C196NU USER’S MANUAL The device ent ers idle mode after exec utin g the IDLPD # 1 instruct ion. A ny enabled inter rupt sour ce, eithe r internal or exter nal , o r a hardware rese t can cause t he devi ce to exit idle mode. When an int errupt oc curs, t he C PU clocks res ta rt an d the CP U exe cute s the c o rre spon din g ...

  • Intel 80C196NU - page 248

    12 -7 SPECIAL OPERATING MODES 12.4.3 Exiti ng S tand by M od e The devic e will exit st andby mode when a transition on an exter nal i nter rupt pin (E XTINT 3:0) or a hardware res et occ u rs. The int errupts nee d not b e e nable d for t hem to bring t he de vice out o f stand b y , but the pi n must be c o nfi gured as a spe c i al-f u nc t i on ...

  • Intel 80C196NU - page 249

    12 -8 8XC1 96NP , 80C196NU USER’S MANUAL After comple tin g these tasks, execut e the IDLPD #2 instruct ion to ente r powerdown mode. NOTE T o prevent an acc ide nta l return to ful l powe r , h old t he exte rnal interrupt pins (EXTI NT x ) l ow while the device is i n powerdown mode. 12.5.3 Exiti ng P ow erd own Mo de The devi ce wi ll e xit po ...

  • Intel 80C196NU - page 250

    12 -9 SPECIAL OPERATING MODES Figure 12-3. Power- up and Powerdown Sequenc e When Using an External Interrupt When using an external interrupt signal to ex i t powerdown mode, we recommend that you con- nect the e xternal com ponent shown i n Fi gure 1 2-4 t o t he RPD pin. The di scha rg ing of the c apac- itor cause s a delay t h a t al lo w s th ...

  • Intel 80C196NU - page 251

    12 -10 8XC1 96NP , 80C196NU USER’S MANUAL During normal operation (before entering powerdown mode), an internal pull-up holds the RPD pin at V CC . Whe n a n ext ernal inte rrupt signa l is ass erted, the int ernal osc i l lator circuit ry is enabled and t u rns on a we ak inte rnal pull - down. The re sis tance of t he inte rnal pull -d own shou ...

  • Intel 80C196NU - page 252

    12-11 SPECIAL OPERATING MODES Fig ure 12-5. T ypical V ol tage on th e RPD Pin W hile E xit ing Powerdown When sele c ting the c apacito r , determ ine the wo r s t-case di scharge time ne eded for the osci llator to stabilize, t hen use this form ula to calculate an appropria te va lue f or C 1 . where: C 1 is th e ca pacito r val ue , in f ara ds ...

  • Intel 80C196NU - page 253

    12 -12 8XC1 96NP , 80C196NU USER’S MANUAL For exampl e, assume t hat t he osc illato r nee ds at least 12. 5 ms t o disc harge (T DI S = 12. 5 m s), V t is 2.5 V , and the discha rge c u rrent is 200 µ A. The mi nim um C 1 ca pa ci t or siz e is 1 µ F. When using a n external osc illator , the va lue of C 1 can be very smal l, a llowing rapid r ...

  • Intel 80C196NU - page 254

    12-13 SPECIAL OPERATING MODES T abl e 12-3. 80C 1 96NU Clock Modes PLLEN 2 PL LEN1 Mode 0 0 Clock-mu lt iplie r circui try d isable d. 0 1 Reserved . CAUTION: T his com bin ation cau ses the device to ente r an unsup p orte d test mo de. 1 0 Do ub led; clock doubling circu itry e nabled. I nternal clock is twi ce the XT AL1 in put. 1 1 Qu ad rupled ...

  • Intel 80C196NU - page 255

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  • Intel 80C196NU - page 256

    13 Interfacing with External M emory ...

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  • Intel 80C196NU - page 258

    13 -1 CHAPTER 13 INTERFAC ING WIT H EXTERN AL MEMORY The device can interfac e wi th a vari ety of exte r nal memory devic es. Six chip-se lect s can be in d i- vidually programm ed f or bus width, t he number of wai t state s, and a mult iple xed o r demul ti- plexed address/data bus. Other f eature s of t he external memory inter f ace incl ude r ...

  • Intel 80C196NU - page 259

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -2 13.2 EX TERNAL M EMORY INTERF ACE S IGNALS T abl e 13-2 desc ribe s the ext erna l memory inte r face sig nals. For some signal s, the pin has a n al- t er n a te f unc tio n (sho w n i n th e Mult ipl ex ed W i th col umn). In some case s the alternat e f unction is a port signal (e.g. , P2.7). Chapt er 7 ...

  • Intel 80C196NU - page 260

    13 -3 INTERFACING WITH EXTERNAL MEM ORY ALE O A ddress La tch Ena ble Thi s acti ve-hi gh o utput sign a l i s a s serte d only du rin g exte rnal me mory cycle s. AL E signa ls t he start of an ext ernal bu s cycle a nd ind icat es that valid a d dre s s in f orma tion is available on the system ad dre ss/dat a b us (A 19 :16 a nd AD1 5: 0 f or a ...

  • Intel 80C196NU - page 261

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -4 EA# I Ex ter na l Ac c ess Thi s input de termine s wh ether m emor y accesses to specia l-pu rpose an d prog ra m m e m ory part iti on s (FF2 00 0– FF 2F FFH) are dire ct ed to int ernal or e xternal me mory . The se a ccesses are di recte d to i nternal me mory if EA# is h eld high a n d to external m ...

  • Intel 80C196NU - page 262

    13 -5 INTERFACING WITH EXTERNAL MEM ORY 13.3 THE CHI P -SELE CT UNI T The chip-sel e ct unit provides six outputs, CS5:0#, for selecti ng an externa l device during an ex- ternal b us cycle . During an e xterna l mem ory acces s, a chip-sel ect o utput CS x # is as sert ed if the address falls within the a ddre ss range ass igned to tha t chip-sel ...

  • Intel 80C196NU - page 263

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -6 Figure 13-1 illust rates the devi c e ’ s calcula t i on of a chip-s e l ect outp u t CS x # f or a given external memory add ress. The 12 most -si gnificant bits of the exte rnal ad dress are compared (XOR ed) bit - wise with the 12 l e as t-significant bits (BASE19:8) of the A D DRCOM x r e gi st er. I ...

  • Intel 80C196NU - page 264

    13 -7 INTERFACING WITH EXTERNAL MEM ORY 13.3.1 Defin in g Chip-se lect Add ress Ranges This se ction de scri bes the ADDRC OM x and ADDRM SK x registers and how to se t them up for a desired addres s r ange. T he ADDRCOM x regis ter (Figu re 13-2) and A DDRM S K x regi ster (Fig- ure 13-3) cont rol the a sserti on of each chip-se lect o u tput C S ...

  • Intel 80C196NU - page 265

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -8 ADDRMSK x x = 0 –5 Ad dress: Reset Sta te : Ta b l e 1 3 - 5 The addre ss m a sk (ADDRMS K x ) reg iste r , t ogeth er with the a d dr es s compa re reg iste r , d efi nes the addr es s ran ge th at is a ssig n ed to th e ch ip - se le ct x ou tp ut, C S x #. Th e ad dre s s m a sk r e gi st er dete rm i ...

  • Intel 80C196NU - page 266

    13 -9 INTERFACING WITH EXTERNAL MEM ORY Observe the followi ng restric tio ns i n choosing an a d d ress range for a chip-se lect output : • The addresses in the address range must be contig uous. • The siz e o f the address ran g e must b e 2 n bytes, w h ere n = 8, 9, ..., 20. This c orre spon ds to block sizes of 256 bytes, 51 2 bytes, ... , ...

  • Intel 80C196NU - page 267

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -10 Note that the 3 2-Kbyte address range could not have 4000H as ba se addre ss, for example , because 4000H is not on a 32-Kbyte boundary . “Exampl e of a Chip-select S etup” on page 13- 12 shows anothe r example of setting up the c hip- select unit . 13.3.2 Control ling Wait S tates, Bu s Wi dth, and B ...

  • Intel 80C196NU - page 268

    13-11 INTERFACING WITH EXTERNAL MEM ORY 13.3.3 Chi p-sel ect Uni t Initia l Condi tio ns A chip re set produce s t he fol lowi n g initial con ditions for t he chi p-sele ct uni t: • ADDRMSK x = XFFFH. • ADDRCOM0 = 0F20 H. This asser ts CS0# for th e 256-by t e address ra nge F2000 –F20FFH. • ADDRCOM1–ADDRCOM 5 = X000H. • For the fetch ...

  • Intel 80C196NU - page 269

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -12 Use the follo wi ng sequenc e to i nit i aliz e the chip -sel ect regis ters afte r reset : 1. Initialize c hip-sel ect output 0 : 1.1. C lear ADDRMSK0. 1.2. Write to ADDRC OM 0 to establi sh the desi red base addres s. 1.3. Write to ADDRMS K 0 to es tabl is h the des ired address range . 1.4. Write the d ...

  • Intel 80C196NU - page 270

    13-13 INTERFACING WITH EXTERNAL MEM ORY Figure 13-5. Exampl e Sy stem for Setti ng Up Chi p-select Outputs The loca tion and size of an addre ss range are spe cified by the ADDR COM x regi ster and the ADDRMSK x re gister (see Figure 1 3-2 an d Figure 13-3). T he 8-Kbyte SR AM is assig ned to ad- dress range 7E000– 7FF FFH and uses c hip-select o ...

  • Intel 80C196NU - page 271

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -14 13.4 CHIP CONFIGURAT IO N REG ISTERS AND CHIP CONF IGURATI ON BY TES T w o chip configurat ion re gisters (C C R s) have bi ts tha t set param eters for chip operat i on and ex- ternal bus cycles. The CCR s cannot be access ed by code. They are loaded from the c hip config - uration byte s ( CCB s), which ...

  • Intel 80C196NU - page 272

    13-15 INTERFACING WITH EXTERNAL MEM ORY CCR0 no direct acces s † The chip con figura tion 0 (CCR0) reg iste r e nabl es o r d isab les po werd own and stan dby (80 C1 96 NU only) mo des an d selects the write-co ntro l mode . It a lso co nt ains the bus-con tro l pa ramet ers for fetchi ng chip con fi gurati on byt e 1. 7 0 1 1 WS 1 WS0 DEM UX BH ...

  • Intel 80C196NU - page 273

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -16 Up o n leavin g the reset state, the device is configured for nor mal ope ration. Thi s secti on describe s the state of the chip followi ng reset and summa rizes the st eps in t he configurat ion proc ess. CCR1 no direct ac cess † The chip con fi gurati on 1 (CCR1 ) re gi ster se le cts t he 16-b it or ...

  • Intel 80C196NU - page 274

    13-17 INTERFACING WITH EXTERNAL MEM ORY Following reset , the chip automatic ally fetches the two chip configura tio n byte s. • 83C196NP only . The CCB fe tches a re fr om ex t ernal me mory if EA# = 0 an d from internal ROM i f EA# = 1 . • 80C196NP and 80C196NU only . The CCB f etc hes a re fro m ext ernal memory . (EA # shou ld be ti e d lo ...

  • Intel 80C196NU - page 275

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -18 After RESET# is deas sert ed, t he followi ng pins are ini tiali zed: • The P2.7/ C LKOUT pi n opera tes as CLKOUT (a s duri ng rese t). B e s ure t hat t he C LKOUT signal does not dam age ext ernal ha r dware. • The P3.0/CS 0# p in operates as CS0#, whic h i s asse rted for the CCB fetches . If you ...

  • Intel 80C196NU - page 276

    13-19 INTERFACING WITH EXTERNAL MEM ORY Figure 13-8. Multipl exi n g and Bus Widt h Opt ions Bus Control Address Bits 16–19 Address Bits 0–15 16-bit Data A19:16 (EPORT) A15:0 AD15:0 8XC196 Device Bus Control Address Bits 16–19 Address Bits 0–15 A19:16 (EPORT) A15:0 AD7:0 8XC196 Device 8-bit Data Driven with the data currently ...

  • Intel 80C196NU - page 277

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -20 A design can inco rporate e xternal devi c e s that ope rate with di f ferent bus wi d t hs and m u ltipl e x- ing. The bus parameters use d during a particul ar bus cycle are det erm ine d by t he chi p-sel ec t out- put that is assigned to the ad dress bei ng acces sed. Fig ure 13-9 shows the ad dress a ...

  • Intel 80C196NU - page 278

    13-21 INTERFACING WITH EXTERNAL MEM ORY In mult iplexed m ode , with t he full a d d ress on the bus for only hal f of the cycle , the external de- vic e ha s les s time t o re c e ive it a nd to re spon d. As a re sult , f or the same b us-cycl e len gth (4t ) a multiple xed syst em requi res a fast er exte r nal devi ce ( unless wa it s tates a r ...

  • Intel 80C196NU - page 279

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -22 Figure 13-10. 1 6- bit External Devices in Demult iplexed Mode 13.5.2 16-bi t Bu s Timings Figure 13-1 1 show s i deal ize d 16-bit external -bus timings for the 8XC1 9 6NP . The signal s are di- vided into two g roups: signals for a demultiplexed bus (top) and sig nals for a multiplexed bu s (bottom ). S ...

  • Intel 80C196NU - page 280

    13-23 INTERFACING WITH EXTERNAL MEM ORY Figure 13-1 1. Timings fo r Multiplexed and Demultipl e xed 16-bit Buses (8XC196NP) CLKOUT RD# ALE AD15:0 Address Data WR# A19:0 AD15:0 RD# WR# AD15:0 AD15:0 Data Address Data Data Address Data Address Demultiplexed Multiplexed A2461-02 T RLDV T AVDV T WLWH T QVWH T AVDV T QVWH T WLWH T RLDV CLKOUT ALE Data T ...

  • Intel 80C196NU - page 281

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -24 13.5.3 8-bi t Bu s Tim ings Figure 13- 12 shows i dealize d 8-bit timin gs for the 8XC 196NP . One cyc le is required fo r a n 8-bit read or writ e. A 1 6-bit access re qui res tw o cycl es. The first cycl e acc esses t he lower byte , and the secon d cycl e accesses the u pper byte. Exce pt for req u iri ...

  • Intel 80C196NU - page 282

    13-25 INTERFACING WITH EXTERNAL MEM ORY Figure 1 3-12. Timings for Mul tiplexed a nd Demult iplexed 8-bi t Buses ( 8XC196NP ) CLKOUT ALE Address A19:0 WR# AD7:0 AD7:0 Data Low Address Data Low Address Data Low Address Demultiplexed Multiplexed AD15:8 RD# Data AD7:0 Data WR# AD7:0 Data High Address High Address Address Data Low Address Data Data A24 ...

  • Intel 80C196NU - page 283

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -26 13.5.4 Com p ari son of M ultip lex ed and Demul tip lexe d Buses This se ction compares the tim ings for m ultiplexe d and de mul tiplexed buses . A 16-b it bus is us ed for the comparis on. “8-bit Bus T imings” on page 13-24 compares the 8-bit and 16-bit b use s. In a multipl exed system, where AD15 ...

  • Intel 80C196NU - page 284

    13-27 INTERFACING WITH EXTERNAL MEM ORY When selecting infi nit e wait states, be sure to add externa l hardware to count wait states and re- lease REA D Y wit hin a spe ci fie d period of t ime. Othe rwis e, a de fect ive e xte rnal de vic e could t ie up the addre ss/da ta bus indefi nitely . NOTE Rea d y control i s vali d only f o r exte rnal m ...

  • Intel 80C196NU - page 285

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -28 Figure 13-13. READY T iming Diagram — Mult iplexed Mode T0013-02 T WLW H + 2t T QVW H + 2t T CL Y X (m ax) T AVY V T LH LH + 2t T RL RH + 2t T AV D V + 2t T RLD V + 2 t Address Out Data In Address Out Data Out CLKOUT READY AL E RD# AD1 5:0 WR# AD1 5:0 BHE#, I NST A19 :1 6 CS x # T CL YX (mi n) ( rea d) ...

  • Intel 80C196NU - page 286

    13-29 INTERFACING WITH EXTERNAL MEM ORY Fig ure 13-14. READY T im ing Diagram — Demultiple xed Mode (8XC196NP) T0007-02 T CLYX (ma x ) T AVDV + 2t T WL WH + 2t T AV Y V T LHLH + 2t T RLR H + 2 t T RL DV + 2 t T QVWH + 2t Data Data Valid CLKOUT READY ALE RD# AD15 :0 WR# AD15 :0 BHE#, INST A19 :0 CS x # T CLYX (min ) (read) (wr i te) ...

  • Intel 80C196NU - page 287

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -30 Figure 13-15. READY Timing Di agram — Demul tiplexed Mode (80C196 N U) 13.7 BUS-HOLD PRO TO COL The 8XC 196N x supports a bus-hold protocol that allows ext ernal devices to gain control of the address/da ta bus. T he protocol uses three s i gnals, all o f which are p o rt 2 spe cial funct ions: HOLD#/P2 ...

  • Intel 80C196NU - page 288

    13-31 INTERFACING WITH EXTERNAL MEM ORY . Fig ure 13-16. HOLD#, HLDA# Timing When the external devic e is finished wit h the bus, i t relin quishe s co ntrol by driving HO LD# high. In response, t h e 8XC196 N x deassert s HLDA# a n d resumes cont rol of the bus. T able 13-12. HOLD#, HLDA# Timing Defini tions Sy mb ol P ara me ter T HVC H HOLD# Set ...

  • Intel 80C196NU - page 289

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -32 If the 8XC196N x has a pending externa l bus cycle while i t is in hold (an other device has control of the bus), it asserts BREQ# to reque st control of the bus. Aft er the exte rnal device responds by releasing H OLD#, the 8XC1 96N x e xits hold and t hen de ass erts BR EQ# a nd HLDA #. 13.7.1 E nab lin ...

  • Intel 80C196NU - page 290

    13-33 INTERFACING WITH EXTERNAL MEM ORY 13.7.4 Rega in ing Bus Control While HO LD# is a sserted, the 8 XC1 9 6 N x c ontin u e s exe cuting code until it nee ds to a c cess the external bus. If e xecuting from i nte r n al memor y , it cont inues u ntil it needs t o perform an ext ernal memory cycl e. If execut ing fr om external m emory , it cont ...

  • Intel 80C196NU - page 291

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -34 Figure 13-17. W rite-contr ol Sig n al W av eform s T abl e 13-14 compares the values of the write-c o ntrol signal s for wri te operatio ns in the st a ndard mode and the wri te strobe m ode. The table lists values of WR # and BHE # and value s of WRL # and WRH# for 8-bit and 16-bit writes on an 8-bit an ...

  • Intel 80C196NU - page 292

    13-35 INTERFACING WITH EXTERNAL MEM ORY T o writ e si ngl e byt es on a 16-b it b u s requires separa te low-byte and hig h-byte write signal s (WRL# a n d W RH#). Figure 13- 18 shows a s a mple c i rcuit that combi nes WR#, BHE#, and ad- dress b it 0 (A0) to produce these signals. This ad ditional logic is unnecessary , however . In the write stro ...

  • Intel 80C196NU - page 293

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -36 Figure 13-19 i l lust rat es the use of th e write strobe mode in a mixed 8-bit a nd 1 6-bit system with two flash me mori es and one SRAM. The W RL# signal , which i s generated for all 8-bit writes (T abl e 13 -14 ), is use d to wri te byte s t o the SRAM . Not e that t he RD# si gnal is su fficient for ...

  • Intel 80C196NU - page 294

    13-37 INTERFACING WITH EXTERNAL MEM ORY Figure 13-20. Multiplexed System Bus T iming ( 8XC196NP ) CLKOUT ALE RD# AD15:0 (read) WR# AD15:0 (write) BHE#, INST AD15:8 T CLCL Address Out Data Data Out Address Out Address Out T CHCL T LHLL Valid A2367-05 T CLLH T RLCL T LLCH T LHLH T LLRL T RLRH T RHLH T AVLL T LLAX T RLDV T RHDZ T RLAZ Address ...

  • Intel 80C196NU - page 295

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -38 Figure 13-21. Multiplexed System Bus Timing (80C1 96NU) T0011-02 T CLCL T CL LH T LHLL T RL AZ T RHDZ T AV L L T WLW H T CHWH T WH LH T QV W H T WHB X , T RHB X T T RLC L T T CHDV T LH LH T LL C H T LLRL T RHLH T RL RH T AVDV T LLA X T RL DV T LLWL T WH QX T WH AX ,T RHAX T WHSH ,T RHSH Address Out Data I ...

  • Intel 80C196NU - page 296

    13-39 INTERFACING WITH EXTERNAL MEM ORY Figure 13-22. Demultiplexed System Bus T im ing ( 8XC196NP )  CLKOUT ALE RD# AD15:0 (read) WR# AD15:0 (write) BHE#, INST A19:0 CS x # T CLCL Valid Valid Address Out T CHCL T LHLL Valid A2368-05 T CLLH T CLDV T LLCH T LHLH T RLCH T RLRH T RHLH T RLDV T RHDZ T AVDV T WLCH T WLWH T WHLH T QVWH T W ...

  • Intel 80C196NU - page 297

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -40 Figure 13-23. Demultiplexed System Bus T im ing (8 0C1 96NU) 13.9.1 Deferre d Bus-cycle Mode (80C196NU Only) The 80C 196NU offers a deferred bus cyc le mode. This bus mo de (enabled b y CCR1.5; see Fig u re 13-7 on page 13-16) reduces bus co ntention when using t he 80C196NU in demultiplexed m ode with sl ...

  • Intel 80C196NU - page 298

    13-41 INTERFACING WITH EXTERNAL MEM ORY Figure 13-24. Deferred Bus-cycle Mode Timing Diagram (80C196NU) T LH LH + 2 t T WHLH + 2t T RHL H + 2 t T AVRL + 2 t T AV D V + 2t T AVWL + 2 t val id valid valid CLKOUT AL E RD# AD1 5:0 WR# AD1 5:0 BHE#, I NST A19 :1 6 CS x # T0010-02 (re ad) (writ e) ...

  • Intel 80C196NU - page 299

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -42 13.9.2 Expl anati on o f AC Sym bo ls Each s ymbol consis ts of t wo pai rs of letters prefixe d by “T” (for time). The cha rac ters i n a pai r indicat e a signal and it s condit ion, respec ti vely . Symbols re pre sent the t im e bet wee n the tw o sig- nal/condition points. For e xample, T LLR L i ...

  • Intel 80C196NU - page 300

    13-43 INTERFACING WITH EXTERNAL MEM ORY The 8 XC1 96N x Meets Thes e Spe ci fic atio ns f Op e ra ti ng fr e qu en cy Freq uency of the signal in pu t o n the XT AL1 p in times the clock multip lier ( x ). For th e 8XC1 96 NP , x is always 1 ; for t he 80C196NU, x is 1 , 2, or 4, de pendi ng on th e cl oc k mode . T he i nte rn al bu s spee d of th ...

  • Intel 80C196NU - page 301

    8XC1 96NP , 80C196NU USER’S MANUAL 13 -44 The 8 XC1 96N x M eets T hes e Spe ci fica tio ns (Con tinu ed ) T RHA X (Mu ltipl exed M ode) AD1 5:8/CS x # Hold after RD# High Minim u m ti m e the h ig h byte of the addre ss in 8 -b it mode will be valid af t er RD# inactive. ( Dem ult i pl exe d Mod e ) A1 9:0 /CS x # Ho ld a fte r RD# Hig h Min imu ...

  • Intel 80C196NU - page 302

    13-45 INTERFACING WITH EXTERNAL MEM ORY The 8 XC1 96N x M eets T hes e Spe ci fica tio ns (Con tinu ed ) T WHSH A1 9: 0 /CS x # Ho ld afte r WR # Hi gh Min imu m ti m e the a ddre ss and chip-sel ect ou tput are held after WR# ina ctive. T WLCH WR# Lo w to CL KOUT Hi gh Minimu m a n d maximum t i m e b etween WR# b ein g ass erted and CLKOUT g o in ...

  • Intel 80C196NU - page 303

    ...

  • Intel 80C196NU - page 304

    A Instruction Set Re fer enc e ...

  • Intel 80C196NU - page 305

    ...

  • Intel 80C196NU - page 306

    A- 1 APPENDI X A INST RUCT ION SET REF ERENCE This appe n dix p r ovi des referenc e i nforma t ion for the instruct ion set of the fam i l y of M C S ® 96 microcont rollers. It defines the p r ocess or status word (PSW) flags, des cribes each instruc tion, shows the relatio nships bet ween inst ructions and PSW fla gs, and shows hexade cima l opc ...

  • Intel 80C196NU - page 307

    8XC1 96NP , 80C196NU USER’S MANUAL A-2 T able A -1. Opcode Map ( L eft Half) Opco de x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 0 x SKIP CLR NOT NEG X CH di DEC EXT IN C 1 x CLRB NOTB NEGB XC HB di DECB EXTB INCB 2 x SJMP 3 x JBC b i t 0 b i t 1b i t 2b i t 3b i t 4 b i t 5 b i t 6b i t 7 4 x AND 3op AD D 3o p di im in ix di im i n ix 5 x AN DB 3 op ADDB 3o ...

  • Intel 80C196NU - page 308

    A- 3 INSTRUCTION SET REFERENCE T able A-1. O pcode M ap (Right H alf) Opco de x 8 x 9 x A x B x C x D x E x F 0 x SHR SHL SHRA XCH ix SHRL SHLL SHRAL NORM L 1 x SHRB SHLB SHRAB XCHB ix EST in EST ix ESTB in ES TB ix 2 x SCAL L 3 x JBS b i t 0 b i t 1b i t 2b i t 3b i t 4 b i t 5 b i t 6b i t 7 4 x SUB 3o p MU LU 3o p (N ote 2 ) di im in ix di im i ...

  • Intel 80C196NU - page 309

    8XC1 96NP , 80C196NU USER’S MANUAL A-4 T able A-2. Processor S t atus Word (PSW) Flags Mne m oni c De scripti on C T he carry flag i s set to i nd icat e a n arith metic carr y fr o m th e M SB of the ALU o r the state o f t he la st b it sh ift ed ou t of an op era nd . If a sub tracti on op era ti on ge ne rate s a b orro w , the carr y fl ag i ...

  • Intel 80C196NU - page 310

    A- 5 INSTRUCTION SET REFERENCE T abl e A-3 sh ows the eff ect o f the PSW fl ags or a specified condit ion on condi tio n al jump inst ruc- tions. T able A-4 define s t he symbol s used in T able A-6 to show th e effect of e ach instructio n on the PSW flags. . T able A- 3. Effect of PSW Flags or Specifi ed Conditi on s on Condit ional Jump Instruc ...

  • Intel 80C196NU - page 311

    8XC1 96NP , 80C196NU USER’S MANUAL A-6 T abl e A-5 defines the vari abl es that are used in T able A-6 t o repre se nt t he inst r uct ion operan ds. T able A- 5. Operand V ariables V aria bl e Des cri ptio n aa A 2-b it fie ld wit hin a n o pco de th at se lects th e ba sic a ddre ssing mode use d. Thi s fie ld is pr esen t only in th ose op cod ...

  • Intel 80C196NU - page 312

    A- 7 INSTRUCTION SET REFERENCE T able A- 6. Instructi o n Set Mne mo nic Operati on Ins truc tion Fo rma t ADD (2 o pe ran d s) ADD WORDS. Adds the source a n d destin at ion wo rd op er ands a nd store s th e sum i nto th e de st in ati on o pe ran d. (DEST) ← (DEST ) + (SRC) D EST , SRC A DD w reg , wa op (0 1 1 00 1a a) ( wao p) ( wre g) P SW ...

  • Intel 80C196NU - page 313

    8XC1 96NP , 80C196NU USER’S MANUAL A-8 A DDCB ADD BY TES WITH CA R RY . A dds the sou rce and de stin ation b yte o p erands and t he carry f lag (0 o r 1 ) a nd st ores th e s um in to th e destin at io n ope ra nd . (DEST) ← (DEST ) + (SRC) + C D EST , SRC A DD CB bre g, baop ( 101 101 aa ) (b ao p) (bre g ) P SW F lag Se ttin gs ZN CV V T S ...

  • Intel 80C196NU - page 314

    A- 9 INSTRUCTION SET REFERENCE AND B (3 o pe ran d s) L OGICAL AND BY TES . ANDs the two sou r ce byte o pe rands a nd sto res th e resu lt into t he destin at io n ope ra nd . The resu lt ha s ones in only t he bit p osi tions i n wh ich bo th oper ands had a “1” and zeros in all othe r bit positio ns . (DEST) ← (SRC1) AND (SRC2) D EST , SRC ...

  • Intel 80C196NU - page 315

    8XC1 96NP , 80C196NU USER’S MANUAL A-10 B MOVI INT ERRUPTIBL E B LOCK MOV E. Mo ves a block of word data fro m o n e l ocat io n i n memo r y to a n oth e r . The inst ructio n is identi cal t o BMOV , excep t that BMOVI is inte rrup ti ble. The source an d d esti natio n add resses are calcul ated usin g the in d irect wit h au toincre me nt ad ...

  • Intel 80C196NU - page 316

    A-11 INSTRUCTION SET REFERENCE CLR CLEAR W ORD. Cl ea rs the va lu e of the ope ran d. (DEST) ← 0 DE S T CL R w reg ( 000000 01) (wre g) P SW F lag Se ttin gs ZN CV V T S T 1000 — — CL RB CL EAR B YTE. Cle ar s t he val ue of th e ope ran d. (DEST) ← 0 DE S T CL RB b re g (0 0010 001) (br e g) P SW F lag Se ttin gs ZN CV V T S T 1000 — ? ...

  • Intel 80C196NU - page 317

    8XC1 96NP , 80C196NU USER’S MANUAL A-12 CMPB COM P ARE BYT ES. Sub tract s the sou rce byte o peran d fro m the desti natio n byte op era nd . The fl ag s ar e al te r ed , but th e ope ran ds re main u naffecte d. If a b orro w occurs, the carry fl a g is c l eare d; ot her wise, it is set. (DEST) – (SRC ) D EST , SRC CM PB b re g, baop ( 1001 ...

  • Intel 80C196NU - page 318

    A-13 INSTRUCTION SET REFERENCE DI DIS ABL E INT ERRUPTS. Disab les inte rrup ts. Interru pt call s cannot occur after this i nstru ct ion. Inte rrup t E na bl e (P SW .1 ) ← 0 DI ( 11111 0 1 0 ) P SW F lag Se ttin gs ZN CV V T S T ———— —— DIV DIV IDE I NTEGERS . Divi des the con tent s of th e de st ina ti on long-i nte ger op e ra nd ...

  • Intel 80C196NU - page 319

    8XC1 96NP , 80C196NU USER’S MANUAL A-14 DIVU DIVIDE W ORDS, UNSIGNED. Divid e s the con tents o f t he destin at ion d oub le- wor d ope rand by the cont ent s o f t h e source word ope ran d, usin g un sign ed arith m etic. It store s th e qu oti en t i nt o t he lo w- o rde r wo rd ( i.e ., the w ord wi t h t he l o we r ad dres s) of th e dest ...

  • Intel 80C196NU - page 320

    A-15 INSTRUCTION SET REFERENCE DJNZW DECRE MENT A ND JUMP IF NOT Z ERO WORD. Decrements the va lue of the word operand by 1. If the result is 0, control passes to th e next se quentia l instru ct ion. If the resul t is n ot 0, th e instru ctio n adds to the pro gra m cou nter t he offse t b etwe en th e en d of this instructi on a nd th e targ et l ...

  • Intel 80C196NU - page 321

    8XC1 96NP , 80C196NU USER’S MANUAL A-16 EBM OVI EXT ENDED INTE RRUPT ABL E BLOCK MOVE. M o ves a bl ock of word d ata from on e memo r y location to anot her . Th is instru ct io n all ows you to m ove b locks of u p t o 64 K w ords betwe en a ny tw o l ocat io ns in th e 16 -M byte address space. T his i nstru ctio n is in te r- ru pta bl e. The ...

  • Intel 80C196NU - page 322

    A-17 INSTRUCTION SET REFERENCE E CALL EXT ENDED CAL L. Pushe s the conten ts of th e pro gra m counte r (t he re turn add ress) o nto th e st ac k, th en a dd s to the p rog ram cou nter t he offse t b etwe en th e en d of this instructi on a nd th e targ et la bel, effe ct ing t he cal l. The o pe ran d may be a ny address in the address space. Th ...

  • Intel 80C196NU - page 323

    8XC1 96NP , 80C196NU USER’S MANUAL A-18 ELD EXT ENDED LOAD WORD. Loads the value of th e source wor d o pera nd into th e destin at io n ope ra nd . This i nstru ct ion al low s you to m ove da ta fro m anywhe re in the 16-M byt e addre ss sp ace into the lower reg ister f ile. ext. in direct: (DEST ) ← (SRC) ext indexed: (DEST) ← (S RC) + 24 ...

  • Intel 80C196NU - page 324

    A-19 INSTRUCTION SET REFERENCE EST EXTENDED STOR E WORD. S t ores th e val ue of the source (le ftmo st) word o peran d in to th e de st ina ti on (rig htm os t) op era nd . This i nstru ct ion al low s you to m ove da ta fro m the lower reg ister f ile to anywh ere in the 1 6- Mbyte a ddress space. ext. in direct: (DEST ) ← (SRC) ext indexed: (D ...

  • Intel 80C196NU - page 325

    8XC1 96NP , 80C196NU USER’S MANUAL A-20 EXTB SIGN- EXTE ND SHORT-INTEGER INTO INTEGER. Sig n-exten ds the low-o rde r b yte of the operan d throu gh ou t the high-o rd er byte o f th e op e ra nd . if DES T .7 = 1 th en (hig h byte DEST) ← 0 FFH else (hig h byte DEST) ← 0 en d_ if EXTB w reg ( 000101 10) (wre g ) P SW F lag Se ttin gs ZN CV V ...

  • Intel 80C196NU - page 326

    A-21 INSTRUCTION SET REFERENCE IN C INCREME NT W ORD. I ncrem ents t he val ue of the word ope ran d by 1. (DEST) ← (DEST) + 1 I NC w reg (0 0000 1 1 1) ( wre g) P SW F lag Se ttin gs ZN CV V T S T ✓✓✓✓ ↑ 0 IN CB INCRE MENT B YTE. In crem ents th e va lue o f the byte op eran d b y 1. (DEST) ← (DEST ) + 1 INCB b re g (0 0010 1 1 1) ( ...

  • Intel 80C196NU - page 327

    8XC1 96NP , 80C196NU USER’S MANUAL A-22 JC JUMP IF CARRY FL AG I S SE T . T ests the carry fla g. If t he carry fl ag i s clea r , con trol pa sses to th e n e xt se quen ti al in structi on . If the carry fl ag is set , th is i nstruct ion a dds to the pro gra m cou nte r t he offset be twe en the end of this in structi on a nd th e targ et la b ...

  • Intel 80C196NU - page 328

    A-23 INSTRUCTION SET REFERENCE JGT JUMP IF SIGNE D GREA TER T HAN. T ests b oth the ze ro fla g an d the n egati ve f la g. If eith er flag is set, control pas ses to th e next seq uent ial i nstru ct ion. I f b ot h fla gs a re cle a r , this instru ct ion adds to the progra m counte r the offset be twe en the e nd of this instru ctio n and th e t ...

  • Intel 80C196NU - page 329

    8XC1 96NP , 80C196NU USER’S MANUAL A-24 JL T JUMP IF SIGNE D LE SS T HAN. T ests th e neg ati ve fl ag. I f t he fla g is cl e ar , cont rol pa sses to th e n e xt se quen ti al in structi on . If the nega tive flag is set , this i nstru ct ion add s t o th e pr ogr am co unt er th e offs et b e tw een t he end of this in structi on a nd th e tar ...

  • Intel 80C196NU - page 330

    A-25 INSTRUCTION SET REFERENCE JNH JUMP IF NOT HIGHER (UNS IGNED). T ests both the zero f lag and the carry f lag. If t he carry f lag i s set a nd the zero flag is cle ar , con trol p asses to th e next seq uential instructi on. If either the carr y fl a g is clea r or the zero flag is set, this instru ctio n a dds to the prog ram co un ter the o ...

  • Intel 80C196NU - page 331

    8XC1 96NP , 80C196NU USER’S MANUAL A-26 JNVT JUMP IF OVERF LOW-TRA P FLAG I S CL EAR. T ests the overf low-tra p flag. If the flag is set , this i nstru ctio n cl ea rs the flag and pa s ses con trol to th e ne xt seq ue nti al instructi on. If the over flow-tra p flag i s c lea r , this instru ct ion adds to the progra m counte r the offset be t ...

  • Intel 80C196NU - page 332

    A-27 INSTRUCTION SET REFERENCE JVT JUMP IF OVERF LOW-TRAP FL AG I S SE T . T e sts the overf low-tra p flag. If the flag is clear , con trol p asses to th e next seq uential instructi on. If the ove rflow-t rap flag i s set, th is instructi on cle ars th e flag and adds to th e prog ram co un ter the o f f set bet wee n the end of th is i nstru ct ...

  • Intel 80C196NU - page 333

    8XC1 96NP , 80C196NU USER’S MANUAL A-28 LDB L OAD BYTE. Lo ads the value of the source byte o pe ran d into the desti natio n opera nd. (DEST) ← (SRC) D EST , SRC LD B b re g, ba op ( 101 100 aa ) (b ao p) (bre g ) P SW F lag Se ttin gs ZN CV V T S T ———— —— LDBSE L OAD BYT E S IGN-EXT ENDED. Sign- exte nds th e valu e of t he sou r ...

  • Intel 80C196NU - page 334

    A-29 INSTRUCTION SET REFERENCE MUL (2 o pe ran d s) M UL T IPL Y I NTEGE RS. M u ltipl ies t he sou r ce and de stin ation i nteg er op era nd s, u si ng sig ned arith metic, an d sto res t he 3 2-b it re sult in to th e de st ina ti on lo ng-i nte ger op e ra nd . T he s tic ky bi t f l ag i s unde f ined a fte r th e instructi on i s execut ed . ...

  • Intel 80C196NU - page 335

    8XC1 96NP , 80C196NU USER’S MANUAL A-30 MULB (3 o pe ran d s) M UL T IPL Y S HO RT -I NTEGERS. M ultiplies the two so ur ce s h ort-i nte ger op e ra nd s , usi ng si gn ed a rit hm etic, an d sto res th e 16 -bit resu lt into the desti natio n inte ge r op er and . T he s tic ky bi t f l ag i s unde f ined a fte r th e instructi on i s execut ed ...

  • Intel 80C196NU - page 336

    A-31 INSTRUCTION SET REFERENCE MULUB (2 o pe ran d s) M UL T IPL Y B YTE S, UNS IGNED. Mult iplies the source a n d destin ation o peran ds, usin g unsig ne d a rithm etic, a nd sto res th e word result int o the d estinat ion oper and. The sticky bit f lag i s unde fine d afte r t he inst ructi on is ex ec uted . (DEST) ← (DEST ) × (SRC) D EST ...

  • Intel 80C196NU - page 337

    8XC1 96NP , 80C196NU USER’S MANUAL A-32 NORML NORM ALIZE LONG-INT EGER. Norma lize s the source (leftm ost ) lon g-i nte ger op e ra nd . (Th at is, i t shift s the operan d to the left unti l its most sig nifican t b it is “1 ” o r unti l it h as perfo rm ed 3 1 sh ift s). If th e m o st sign if ican t bit i s stil l “0 ” a fte r 3 1 sh ...

  • Intel 80C196NU - page 338

    A-33 INSTRUCTION SET REFERENCE OR L OGICAL OR WORDS. ORs t he source word ope ran d with the de st ina ti on wo rd o pe ra nd and repl aces the orig inal de stin ation o pera nd wit h the result. T he resul t has a “1 ” in ea ch bit positi on in wh ich ei the r t he sou r ce o r destin at ion o pe ra nd ha d a “1”. (DEST) ← (DEST ) OR (S ...

  • Intel 80C196NU - page 339

    8XC1 96NP , 80C196NU USER’S MANUAL A-34 P OP A POP ALL . T his instr uctio n is used inste ad of POPF , to sup port t he eigh t ad ditio nal inte rrup ts. I t pop s two wo rd s off th e stac k and place s the first word into the INT _MASK 1/W SR register pa ir and the secon d word into t h e PSW/INT _M ASK regi ster-p ai r . Th is i nstru ctio n ...

  • Intel 80C196NU - page 340

    A-35 INSTRUCTION SET REFERENCE P USHA PUS H ALL. Thi s instru ctio n is used inste ad of PUS HF , to su p po rt the eig ht addi tio na l inte rrup ts. I t pushe s two wo rds — PSW /IN T_MAS K a nd INT _M ASK 1/WSR — o nto th e st a c k. This i nstru ct io n cle ar s the PSW, INT_M AS K, and INT _MASK1 re gi sters a nd d ecrem ents the SP by 4 . ...

  • Intel 80C196NU - page 341

    8XC1 96NP , 80C196NU USER’S MANUAL A-36 RS T RES ET S YSTE M. Initial izes the PSW to zero , the EPC /P C to FF 2080 H, a nd th e pins a nd SF Rs to th e ir reset value s. Executin g t his instructi on cau se s th e RESET # p in to be pull ed l ow f or 16 stat e t im es. SF R ← Re set Sta tus Pi n ← Rese t St atus PSW ← 0 EPC/PC ← FF2 08 ...

  • Intel 80C196NU - page 342

    A-37 INSTRUCTION SET REFERENCE S HL SHI F T WORD LEF T . Shif ts the d esti natio n w or d ope ran d t o t he l eft as ma ny ti mes as spe cified by th e coun t opera nd. T he cou nt may b e specif ied eith er as a n im med iate val ue in the ran ge of 0 to 15 (0F H), i nclu sive , or as t he con tent o f an y reg ister (10H – 0FFH) with a val ue ...

  • Intel 80C196NU - page 343

    8XC1 96NP , 80C196NU USER’S MANUAL A-38 SHLL SHI F T DOUBLE -WORD LEF T . Shifts the destin at io n d ou ble- word o peran d t o the le ft as ma ny ti m es a s specif ied b y the cou nt ope rand. Th e co unt m ay b e sp ecif ied e it her as a n imm edia te v al ue in th e ra ng e of 0 to 15 (0FH), in clusive, or as t he content o f any re giste r ...

  • Intel 80C196NU - page 344

    A-39 INSTRUCTION SET REFERENCE SH RA ARI THMETI C RIGHT SHIF T W ORD. S hifts t he d es tin at ion wor d op eran d t o t he r i gh t a s many time s as spe cifie d by th e coun t ope rand. Th e co unt m ay b e sp ecif ied e it her as a n imm edia te v al ue in th e ra ng e of 0 to 15 (0FH), in clusive, or as t he content o f any re giste r (10 H ? ...

  • Intel 80C196NU - page 345

    8XC1 96NP , 80C196NU USER’S MANUAL A-40 SH RAL ARI THMETI C RIGHT SHIF T DOUB LE- WORD. Sh ifts the d esti nation doub le-word op era nd to th e r ig h t as man y time s as spe cified by th e coun t opera nd. T he cou nt may b e specif ied eith er as a n im med iate val ue in the ran ge of 0 to 15 (0F H), i nclu sive , or as t he con tent o f an ...

  • Intel 80C196NU - page 346

    A-41 INSTRUCTION SET REFERENCE SH RL LOGI CAL RIGHT SHIF T DOUBLE-W ORD. Sh ift s th e de st inati on d ou ble-wo rd ope ran d to t he r igh t as ma ny t ime s as s pec if ied by th e cou nt op era nd. The cou nt may b e sp ecifi ed eith er a s an im medi at e valu e in the ran ge of 0 to 1 5 ( 0 FH ) , in clu si ve , o r a s the c on te nt of any ...

  • Intel 80C196NU - page 347

    8XC1 96NP , 80C196NU USER’S MANUAL A-42 ST STORE W ORD. S tore s th e va lu e o f t he sou r ce (l eftm os t) w o rd op e ra nd i nt o th e destin at io n ( ri ght mo st) op era nd . (DEST) ← (SRC) SRC, DE ST S T w reg , wa op (1 10 000a a) ( wao p) ( wre g) P SW F lag Se ttin gs ZN CV V T S T ———— —— S TB STORE BYT E. Sto res the v ...

  • Intel 80C196NU - page 348

    A-43 INSTRUCTION SET REFERENCE SU BB (2 o pe ran d s) SUB TRACT BYT ES. Sub tract s the sou rce byte o peran d fro m the desti natio n byte ope ran d, store s th e re sul t in the destin ati on ope rand, and sets th e ca rry fl ag as t he com plem ent of bo rro w . (DEST) ← (DEST ) – (SRC) D EST , SRC S UB B b re g, ba op (0 1 1 1 10 aa) (bao p ...

  • Intel 80C196NU - page 349

    8XC1 96NP , 80C196NU USER’S MANUAL A-44 TIJMP T ABLE INDI RECT JUMP . Causes exe cuti on t o c ont inu e at an a ddr ess s el ect ed fr om a ta bl e of ad dre ss e s. The first word regist er , TBAS E, contain s the 16 -bi t a ddr ess of th e be gi nni ng of the jump tabl e. TBA SE can b e loca ted i n RA M up to FE H witho ut win dowin g or a bo ...

  • Intel 80C196NU - page 350

    A-45 INSTRUCTION SET REFERENCE TR AP SOF TWARE TRAP . T his i nstru ctio n causes an int erru pt call that is vecto red th roug h locati on FF 2010 H. T he o pe rat ion o f t hi s instructi on i s n ot a ffected b y the sta te of the inte rrup t en ab le flag (I) i n the PSW. I nt erru pt c all s ca nnot oc cur i mme di atel y fol l ow i ng thi s i ...

  • Intel 80C196NU - page 351

    8XC1 96NP , 80C196NU USER’S MANUAL A-46 T able A-7 l i sts the instruction opcodes, in he xadecimal order , along wi th the corresponding i n- structio n mnemonic s. X OR L OGICAL EXCL USIV E-OR WORD S. XORs the sou rce wo rd op e rand wit h th e desti na tion wo rd o p era nd a nd st ore s th e re sul t in t he destin at io n ope ra nd . The res ...

  • Intel 80C196NU - page 352

    A-47 INSTRUCTION SET REFERENCE T able A -7. Inst ructi on Opcodes He x Co de Ins truc tion M nemon ic 00 SKI P 01 CLR 02 NOT 03 NEG 04 X CH Dire c t 05 DEC 06 EXT 07 INC 08 SHR 09 SHL 0A S HR A 0B X CH In de xe d 0C S HR L 0D S HLL 0E SHRAL 0F NORM L 10 Re served 11 C L R B 12 NOT B 13 NEGB 14 X CHB Di rect 15 DE CB 16 EXT B 17 INC B 18 SHRB 19 SHL ...

  • Intel 80C196NU - page 353

    8XC1 96NP , 80C196NU USER’S MANUAL A-48 44 A DD Dire ct (3 o ps) 45 ADD I mme di ate (3 o ps) 46 A DD In direct ( 3 ops) 4 7 A DD In de xe d ( 3 op s) 48 S UB Di rect (3 o ps) 49 SUB Imme diat e ( 3 o ps) 4A S UB Indi rect (3 op s) 4B S UB In de x ed (3 op s) 4C MUL U Dir ect (3 op s) 4 D MU LU I mme di ate (3 o ps ) 4E MUL U In direct ( 3 o ps) ...

  • Intel 80C196NU - page 354

    A-49 INSTRUCTION SET REFERENCE 6 D MU LU I mme di ate (2 o ps ) 6E MUL U In direct ( 2 o ps) 6F MULU I nd exed ( 2 ops ) 70 A NDB Di rect (2 o ps) 71 ANDB Imm e diat e (2 o ps) 72 A NDB Indirect (2 ops) 73 A NDB In de xed (2 op s) 74 A DDB Di rect (2 o ps) 75 ADDB Imm e diat e (2 o ps) 76 A DDB Indirect (2 ops) 77 A DDB In de xed (2 op s) 78 S UBB ...

  • Intel 80C196NU - page 355

    8XC1 96NP , 80C196NU USER’S MANUAL A-50 97 X OR B In de x ed 98 CM PB Dire c t 99 CMP B Imm e di ate 9A CM PB In di r ect 9B CM PB In de xe d 9C DI VUB Di rect 9D DI VUB I mme diate 9E DIVUB I nd irect 9F DI VUB I ndexed A0 LD Di rect A1 LD I mme di ate A2 L D In di re ct A3 L D In de xe d A4 A DDC Dir ect A5 ADD C I mme diat e A6 AD DC Indi rect ...

  • Intel 80C196NU - page 356

    A-51 INSTRUCTION SET REFERENCE C0 S T Di rect C1 BMOV C2 S T Indi rect C3 S T In de xe d C4 S TB Di rect C5 CMPL C6 STB In di r ec t C7 STB I ndexed C8 P USH Di rect C9 PUS H I mm edi ate CA P USH Indirect CB P US H In de xe d CC P OP Dir ect CD B MOVI CE P OP In direct CF POP I nd exe d D0 JNST D1 JNH D2 JGT D3 JNC D4 JNVT D5 JNV D4 JNVT D5 JNV D6 ...

  • Intel 80C196NU - page 357

    8XC1 96NP , 80C196NU USER’S MANUAL A-52 T able A-8 lists inst ructions along with thei r lengt hs and opc o des for each a pplicable addressing mode. A dash (—) in any column indica tes “n ot a ppli ca ble.” E6 EJMP E7 LJMP E8 EL D In dir ec t E9 EL D In dex ed EA E LDB Indire ct EB E LDB Indexe d EC DPTS ED E PTS EE Re served (Note 1) EF L ...

  • Intel 80C196NU - page 358

    A-53 INSTRUCTION SET REFERENCE T able A-8. Instr uction L e ngths and Hexadecimal Opcodes Ari thm eti c ( Group I) Mn em on ic Direc t Im m edi ate In dire ct (Note 1) In dex e d (N ote s 1, 2) Len gth Opc ode L ength Opco de Le ng th Opcode Le ngth S/ L Opc ode A D D ( 2 o p s ) 36 446 53 6 6 4 / 5 6 7 A D D ( 3 o p s ) 44 454 54 4 6 5 / 6 4 7 AD ...

  • Intel 80C196NU - page 359

    8XC1 96NP , 80C196NU USER’S MANUAL A-54 Arithme tic (Group II ) Mn em on ic Direc t Im m edi ate In dire ct (Note 1) In dex e d (N ote s 1, 2) Len gth Opc ode L ength Opco de Le ng th Opcode Le ngth S/ L Opc ode DI V 4 FE 8C 5 F E 8D 4 FE 8E 5/6 FE 8F DI VB 4 FE 9C 4 FE 9D 4 FE 9E 5 /6 FE 9F DIVU 3 8C 4 8D 3 8E 4/5 8F DIVUB 3 9C 3 9D 3 9E 4/5 9F ...

  • Intel 80C196NU - page 360

    A-55 INSTRUCTION SET REFERENCE S tac k Mn em on ic Direc t Im m edi ate In dire ct (Note 1) In dex e d (N ote s 1, 2) Len gth Opc ode L ength Opco de Le ng th Opcode Le ngth S/ L Opc ode PO P 2 CC — — 2 CE 3/4 CF P O P A 1 F 5 —————— P O P F 1 F 3 ——— ——— PUSH 2 C8 3 C9 2 CA 3 /4 CB P U S H A 1 F 4 —————— P U ...

  • Intel 80C196NU - page 361

    8XC1 96NP , 80C196NU USER’S MANUAL A-56 Data Mn em on ic Direc t Im m edi ate E xte nd ed- ind irec t E xte nde d- in dex e d Len gth Opc ode L ength Opco de Le ngth Op cod e Length Opc od e E B M O V I ———— 3 E 4 —— E L D ———— 3 E 8 6 E 9 E L D B ———— 3 E A 6 E B E S T ———— 3 1 C 6 1 D E S T B ———— 3 1 ...

  • Intel 80C196NU - page 362

    A-57 INSTRUCTION SET REFERENCE Ju mp Mn em on ic Direc t Im m edi ate E xte nd ed- ind irec t E xte nde d- in dex e d Len gth Opc ode L ength Opco de Le ngth Op cod e Length Opc od e E B R ———— 2 E 3 —— E J M P —————— 4 E 6 Mn em on ic Direc t Im m edi ate In dire ct (Note 1) In dex e d (N ote s 1, 2) Len gth Opc ode L ength ...

  • Intel 80C196NU - page 363

    8XC1 96NP , 80C196NU USER’S MANUAL A-58 Con dit ion al Jump Mn em on ic Direc t Im medi ate In dire ct In dex e d (N ote s 1, 2) Len gth Opc ode L ength Opco de Le ng th Opcode Le ngth S/ L Opc ode D J N Z —————— 3 / — E 0 DJNZW —————— 3 / — E 1 J B C —————— 3 / — 3 0 – 3 7 J B S —————— 3 / ...

  • Intel 80C196NU - page 364

    A-59 INSTRUCTION SET REFERENCE Shi ft Mn em on ic Direc t Im medi ate In dire ct In dex e d Len gth Opc ode L ength Opco de Le ngth Op cod e Length Opc od e NORML 3 0 F —————— S H L 3 0 9 —————— S H L B 3 1 9 —————— S H L L 3 0 D —————— S H R 3 0 8 —————— S H R A 3 0 A —————— S ...

  • Intel 80C196NU - page 365

    8XC1 96NP , 80C196NU USER’S MANUAL A-60 T able A-9 lists instruct ions alp h abet ically within groups, along wit h their exec utio n t ime s, ex- presse d i n st at e time s. T abl e A-9. Instr uct ion Execution Times (in State T imes) Ari thm eti c ( Group I) Mne moni c Dire ct I mmed . I ndi rec t In de xe d Norm al Autoin c. Sh ort Long R e g ...

  • Intel 80C196NU - page 366

    A-61 INSTRUCTION SET REFERENCE Arithme tic (Group II ) Mne moni c Dire ct I mmed . I ndi rec t In de xe d Norm al Autoin c. Sh ort Long R e g .M e m .R e g .M e m .R e g .M e m .R e g .M e m . D I V 2 6 2 7 2 83 12 93 22 93 23 03 3 DI VB 18 1 8 20 23 2 1 24 21 2 4 22 25 DI VU 24 2 5 2 6 29 2 7 30 27 30 28 31 DI V UB 16 1 6 18 21 19 22 19 2 2 20 23 ...

  • Intel 80C196NU - page 367

    8XC1 96NP , 80C196NU USER’S MANUAL A-62 Sta ck ( Re gis te r) Mne moni c Dire ct I mmed . I ndi rec t In de xe d Norm al Autoin c. Sh ort Long R e g .M e m .R e g .M e m .R e g .M e m .R e g .M e m . P OP 8 — 1 0 12 1 1 13 11 13 12 14 P O P A 1 2 — — ——— ———— P O P F 7 — — ——— ———— P U S H 6 7 9 1 21 01 31 01 ...

  • Intel 80C196NU - page 368

    A-63 INSTRUCTION SET REFERENCE Data Mne moni c E xtende d-i ndi rect (Norm a l) E BM OVI re gi st er/ reg iste r 8 + 14 p er word + 16 per int erru pt me mo ry/reg iste r 8 + 17 per word + 16 p er i nt erru pt me mo ry/m emo ry 8 + 2 0 p er word + 1 6 per int erru pt Mne m oni c I ndi re ct B MOV re gi ster/ reg iste r 6 + 8 p er word me mory/reg i ...

  • Intel 80C196NU - page 369

    8XC1 96NP , 80C196NU USER’S MANUAL A-64 Ju mp Mne m oni c Dire ct I mm ed. Exten ded-in dire ct Exte nd ed -ind exed Norm al Autoin c. EBR — — 9 — — EJ MP — — — — 8 Mne moni c Dire ct I mmed . Indire ct Ind ex ed Norm al Autoin c. Sh ort Long BR — — 7 7 — — LJMP — — — — — 7 SJ MP — — — — 7 — TIJMP reg i ...

  • Intel 80C196NU - page 370

    A-65 INSTRUCTION SET REFERENCE Call (M emory ) Mne moni c Dire ct I mmed . Exten de d-in dire ct Exte nd ed -ind ex ed Norm al Autoin c. E CALL 1-M byte m od e — — — — 22 Mne moni c Dire ct I mmed . Indire ct Ind ex ed Norm al Autoin c. Sh ort Lon g LCAL L 1-M byte m od e 64- Kbyte m ode —— — — — 1 8 13 RET 1-M byte m od e 64- Kby ...

  • Intel 80C196NU - page 371

    8XC1 96NP , 80C196NU USER’S MANUAL A-66 Con dit ion al Jump Mne moni c Sho rt-Ind ex ed DJ NZ 5 (j um p not ta ken ), 9 (j ump take n) DJNZW 6 (jump not taken), 10 (jump taken) JBC 5 (j ump no t ta ken ), 9 (j um p take n) JBS 5 (j um p not ta ken ), 9 (j ump take n) JC 4 (j um p not ta ken ), 8 (j um p take n) JE 4 (j ump no t ta ken ), 8 (j um ...

  • Intel 80C196NU - page 372

    A-67 INSTRUCTION SET REFERENCE Sp eci al Mne moni c Dire ct I mmed . Indire ct Ind ex ed Norm al Autoin c. Sh ort Long C L R C 2 — — ——— C L R V T 2 — — ——— D I 2 — ———— E I 2 — ———— IDLPD V a li d key Inval id key — — 12 28 — — — — — — — — N O P 2 — ———— R S T 4 — ———— ...

  • Intel 80C196NU - page 373

    ...

  • Intel 80C196NU - page 374

    B Signal Des criptions ...

  • Intel 80C196NU - page 375

    ...

  • Intel 80C196NU - page 376

    B- 1 APPENDI X B SIGNAL DE SCRI PTIONS This appe ndix pr ovides refere nce informat ion for the pi n fu nct ions of t he 8XC1 96NP an d 80 C196NU. B.1 F UNCTI ONAL G ROUP INGS OF S IGNALS T able B-1 l i sts the signal s for the 8XC 1 96NP and 80C1 96 N U, grouped by funct ion. A diagram of each package t hat i s c u rrentl y avai la ble shows the p ...

  • Intel 80C196NU - page 377

    8XC1 96NP , 80C196NU USER’S MANUAL B-2 Figure B-1. 8XC1 96NP 1 00-lead SQFP Package RD# BHE# / WRH# ALE INST READY RPD ONCE V SS  V CC  V SS  A8 A9 A10 A11 A12 A13 A14 A15 NC V SS  XTAL1 XTAL2 V SS  NC P2.7 / CLKOUT AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 V CC ...

  • Intel 80C196NU - page 378

    B- 3 SIGNA L DESCRIPTIONS Figure B-2. 8XC196NP 100 -lead QFP P a ckage V SS  A18 / EPORT.2 A19 / EPORT.3 WR# / WRL# RD# BHE# / WRH# ALE INST READY RPD ONCE V SS  V CC  V SS  A8 A9 A10 A11 A12 A13 A14 A15 V SS  XTAL1 XTAL2 V SS  P2.7 / CLKOUT NC P2.6 / HLDA# P2.5 ...

  • Intel 80C196NU - page 379

    8XC1 96NP , 80C196NU USER’S MANUAL B-4 Fig ure B-3. 80 C 196NU 100-lead SQFP Package RD# BHE# / WRH# ALE INST READY RPD ONCE PLLEN2  V CC  V SS  A8 A9 A10 A11 A12 A13 A14 A15 NC V SS  XTAL1 XTAL2 V SS  V CC  P2.7 / CLKOUT AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7? ...

  • Intel 80C196NU - page 380

    B- 5 SIGNA L DESCRIPTIONS Figure B-4. 80C196 NU 100-lead QFP P a ckage V SS  A18 / EPORT.2 A19 / EPORT.3 WR# / WRL# RD# BHE# / WRH# ALE INST READY RPD ONCE PLLEN2 V CC  V SS  A8 A9 A10 A11 A12 A13 A14 A15 V SS  XTAL1 XTAL2 V SS  P2.7 / CLKOUT V CC  P2.6 / HLDA# P ...

  • Intel 80C196NU - page 381

    8XC1 96NP , 80C196NU USER’S MANUAL B-6 B.2 S IGNAL DE SCRIP T IONS T abl e B-2 define s t he colum ns used in T abl e B-3, which descri bes the si gna ls. T able B -2. Description of Column s of T able B-3 Col umn He ad ing De scripti on Nam e List s the sig na ls, a rra nged a lpha betical l y . Many p ins have two fun ction s, s o th ere a re m ...

  • Intel 80C196NU - page 382

    B- 7 SIGNA L DESCRIPTIONS AL E O A dd r ess La tch E na ble This acti ve-h igh outpu t signal i s assert ed on ly duri ng e xt ernal m emory cycles. ALE signa ls the start of an extern al b u s cycle a n d indica tes that valid a d d ress infor mation is a vailab le on the system ad dress/d ata bus (A 19:16 a nd AD1 5: 0 for a m u ltipl exed bu s; ...

  • Intel 80C196NU - page 383

    8XC1 96NP , 80C196NU USER’S MANUAL B-8 EA# (NP only) I Exter nal Access This input determines w hether memory accesses to special-purpose a nd pro gr am m em o ry pa rtit io ns (FF 2000 –F F2 FFF H) a re di recte d t o i nt ern al or exte rna l mem ory . The se ac cesse s are d i recte d to intern a l memo r y if EA# is held hig h an d to e xte ...

  • Intel 80C196NU - page 384

    B- 9 SIGNA L DESCRIPTIONS HOL D# I Bus Ho ld Re que st An externa l device u ses this active -low inp ut signal to requ est contro l of the bus. Th is pin fu ncti ons as HOLD# o nly if the p in is con fi gured fo r its specia l functio n ( see “Bid ire ctio na l Port Pin Conf ig ura tio ns” on pa ge 7-7) an d t he b us- hold p roto col is e nab ...

  • Intel 80C196NU - page 385

    8XC1 96NP , 80C196NU USER’S MANUAL B-10 P LLEN2: 1 (N U on l y) I Phase-l ocked Lo op 1 a nd 2 Ena ble These in put pins a re used to e na bl e the o n-ch ip clock mul tipli er featu re a nd select e ither the d ou bled o r qu adrupl ed clock spe ed a s fol low s: PLL EN1 PLL EN2 Mode 0 0 st anda rd mode; clo ck m u ltip lier circuitry disab le d ...

  • Intel 80C196NU - page 386

    B-11 SIGNA L DESCRIPTIONS RP D I Ret urn fro m Po werd own Ti m in g pin f or the return -fro m-po wer down cir cu it. If your ap plicati on uses po werd o wn mo de, conne ct a capacito r † be twe en RPD an d V SS if eith er o f t he fo ll owi ng con di tio ns a re true . • the i ntern al oscill ator is th e clo c k source • the p hase-l o ck ...

  • Intel 80C196NU - page 387

    8XC1 96NP , 80C196NU USER’S MANUAL B-12 V CC PWR Dig ita l Sup pl y V ol tag e Con nect e ach V CC pi n to the d ig ita l su pp l y v ol tag e. V SS GND Digita l Circuit Groun d Con nect e ach V SS pi n t o gr oun d t hrou gh th e l owes t p os si ble im peda nce pa th. W R# O Write † This acti ve -lo w outp ut indica tes t hat a n ext ern al w ...

  • Intel 80C196NU - page 388

    B-13 SIGNA L DESCRIPTIONS B.3 DE F AULT CO NDIT IO NS T abl e B-5 l ist s the default functions of the I/O and contr ol pins of the 8XC 196NP and 80C 196NU with their values during v arious operating co nditions. T abl e B-4 defines the symbols used t o rep- resent t he pin s t a tus. R efer to the DC Charac terist ics tabl e in the datasheet for a ...

  • Intel 80C196NU - page 389

    8XC1 96NP , 80C196NU USER’S MANUAL B-14 P4 .3 — W K1 W K1 (N ot e 1) ( N ot e 1) ( Not e 1 ) — E PO RT .3 :0 A19 :1 6 W K1 1 (N o te 5) (No te 5) (No te 6) (No te 8) — A15 : 0 WK1 L oZ 0 (No te 7) (No te 7 ) H iZ L oZ 0 — AD15 :0 WK1 L oZ0 (No te 7) (No te 7) HiZ LoZ0 — ALE WK0 0 (No te 9) (No te 9) W K0 L oZ0 — BHE# WK1 1 (Note 1 0) ...

  • Intel 80C196NU - page 390

    C Registers ...

  • Intel 80C196NU - page 391

    ...

  • Intel 80C196NU - page 392

    C-1 APPENDI X C REGI STERS This appendix provid es re ferenc e information abou t the d evice registers. T able C-1 lists the mod- ules a nd ma jor c omp onents of the device with thei r re lated configurat ion and stat us regist ers. T a- ble C-2 lists the regist ers , arrange d alpha bet ically b y mnem oni c, along wi th the ir nam es, addresses ...

  • Intel 80C196NU - page 393

    8XC1 96NP , 80C196NU USER’S MANUAL C-2 T able C- 2. Register Name, Address, and R eset Statu s Re gister Mne m oni c Re gis ter Nam e Hex Add ress Bin ary Res e t V al ue High Low ACC_00 (NU) Accumulat or 0 0 00CH 0 000 0 000 0000 0 000 ACC_02 (NU) Accumulat or 2 000EH 0000 0000 0 000 0 00 0 ACC_ST A T (NU) Accum ulat or Cont rol a nd Statu s 000 ...

  • Intel 80C196NU - page 394

    C-3 REGISTERS EP A2 _C ON EP A Captu re /Com p 2 Con tro l 1 F8 8H 000 0 0 00 0 EP A3 _C ON EP A Ca ptu re /Com p 3 Con tro l 1 F8 C H 0 000 000 0 0 00 0 0 000 EP A0 _T IM E EPA Ca ptu re /Com p 0 Time 1 F82 H 0 00 0 0 00 0 0 000 000 0 EP A1 _T IM E EPA Ca ptu re /Com p 1 Time 1 F86 H 0 00 0 0 00 0 0 000 000 0 EP A2 _T IM E E P A Ca ptu re /Com p 2 ...

  • Intel 80C196NU - page 395

    8XC1 96NP , 80C196NU USER’S MANUAL C-4 SBUF _TX Se rial P ort Tr ansmi t Buffer 1FBAH 0000 0 000 SP Stac k Point er 0018H X XXX X XXX X XXX X XXX SP_BAUD Se rial Port Ba ud Rat e 1FBCH 0000 0 000 0000 0 000 SP_ CO N Se ria l P ort Con tro l 1FBB H 0 00 0 0 00 0 SP_ ST ATUS Se ria l P ort Sta tu s 1FB 9H 000 0 1 01 1 T1CONTROL Ti m er 1 Control 1F ...

  • Intel 80C196NU - page 396

    C-5 REGISTERS ACC_0x ACC_0 x x = 0 , 2 (8 0C1 96 N U) Add re ss : Rese t St ate: T a ble C -3 The 32 -b it accum u lator re gi ster (ACC_ 0 x ) re sides a t lo cation s 0C –0FH. Y ou ca n read from or wri te to the ac cumu lator re gi ster a s two wo rds a t locati ons 0CH and 0EH. 80C19 6N U 15 8 Ac cumul ator V alu e (wor d 1 , hig h byte ) 7 0 ...

  • Intel 80C196NU - page 397

    8XC1 96NP , 80C196NU USER’S MANUAL C-6 ACC_ST A T ACC_ST A T (8 0C1 96 NU ) Address: Reset Sta te : 0BH 00H The accum ulato r contro l and statu s (ACC_ ST AT) re gister en ab les and disa bles fract iona l a nd satu ratio n mo des an d cont ains th ree sta tus f lags th at in dica te th e sta tus of the accu mu lato r ’s con tents. 7 0 80C1 96 ...

  • Intel 80C196NU - page 398

    C-7 REGISTERS ACC_ST A T T able C-4. Eff e ct of SME and FME Bi t C ombinati ons SME F ME De scrip tion 0 0 Sets the OVF and STOVF flags if the sig n b it s of the accum ula tor and the adden d (the num be r to b e ad ded to the contents o f t he accum u la tor) are e qual , b ut the sig n bit o f the resu lt is th e op posite . 0 1 S hi fts the ad ...

  • Intel 80C196NU - page 399

    8XC1 96NP , 80C196NU USER’S MANUAL C-8 ADDRCOMx ADDRCOM x x = 0 –5 Address: Reset Sta te : T abl e C- 5 The a d dress co mpare (ADDRCOM x ) re gister sp eci fies the base (lo west) addre ss of t he addre ss rang e. The base addre s s of a 2 n -byte add ress ran ge m ust be o n a 2 n - byte boun dar y . 15 8 — — — — BASE19 B ASE1 8 BAS E ...

  • Intel 80C196NU - page 400

    C-9 REGISTERS ADDRMSK x ADDRMSK x x = 0 –5 Ad dress: Reset Sta te : T abl e C- 6 The addre ss m a sk (ADDRMS K x ) reg iste r , t ogeth er with the a d dr es s compa re reg iste r , d efi nes the addr es s ran ge th at is a ssig n ed to th e ch ip - se le ct x ou tp ut, C S x #. Th e ad dre s s m a sk r e gi st er dete rm ines the size of the add ...

  • Intel 80C196NU - page 401

    8XC1 96NP , 80C196NU USER’S MANUAL C-10 BUSCO Nx BUSCON x x = 0 –5 Ad dress: Reset Sta te : T abl e C- 7 For t h e addres s r an ge assigned to chip-selec t x , the bus control (BUS CON x ) registe r speci fies the num ber o f wait sta tes, th e bu s wid th, a nd th e add ress/data m ultiplexing f or al l exter nal bus cycles tha t access addre ...

  • Intel 80C196NU - page 402

    C-11 REGISTERS CCR0 CCR0 no direct acces s † The chip con figura tion 0 (CCR0) reg iste r e nabl es o r d isab les po werd own and stan dby (80 C1 96 NU only) mo des an d selects the write-co ntro l mode . It a lso co nt ains the bus-con tro l pa ramet ers for fetchi ng chip con fi gurati on byt e 1. 7 0 1 1 WS 1 WS0 DEM UX BHE# BW1 6 PD Bit Num ...

  • Intel 80C196NU - page 403

    8XC1 96NP , 80C196NU USER’S MANUAL C-12 CCR1 CCR1 no direct ac cess † The chip con fi gurati on 1 (CCR1 ) re gi ster se le cts t he 16-b it or 2 4- bit a dd ressing mode and (for the 8XC19 6 NP o nly) co ntr ols wh ethe r th e in terna l ROM is mapp ed i nto two a ddress ra ng es, F F200 0– FF2F FFH an d 0020 00–0 02 FF FH, or into FF2 00 0 ...

  • Intel 80C196NU - page 404

    C-13 REGISTERS CON_REG 0 CON_REG0 A ddress: Reset Sta te : 1F B6H FEH The cont rol (CON_ REG0) registe r contro ls the clo ck presca le r fo r the three p u lse-w idth modu lato r s (PW M0–PWM 2 ). 7 0 8XC19 6NP — — — — — —— C L K 0 † 7 0 80C1 96N U — — — — — — C LK1 C LK0 Bit Num ber Bit Mn em on i c Fun cti on 7:1 (N ...

  • Intel 80C196NU - page 405

    8XC1 96NP , 80C196NU USER’S MANUAL C-14 EP_DIR EP_ DIR Address: Reset Sta te : 1F E3 H FF H In I/O m o de , each b it of the exte nde d p ort I/O d ire ctio n (E P_DI R) re giste r con tro ls th e d ire ctio n of th e corre spond ing pin. Cle aring a bit co nfi gures a pin as a com plemen ta ry out put; set tin g a bi t con figure s a pin a s ei ...

  • Intel 80C196NU - page 406

    C-15 REGISTERS EP_MOD E EP_ MO DE Address: Reset Sta te : 1F E1 H FF H Ea ch bit of the e xten ded po rt mode (EP_ M OD E) regi ster co ntro ls whet he r th e corre sp ondi ng p in functi ons as a standard I/O po rt pin or as an exten ded-add ress sig nal. Sett ing a bit con fi gures a pin as an ext en de d-a dd re ss sig na l; cl ea rin g a bit co ...

  • Intel 80C196NU - page 407

    8XC1 96NP , 80C196NU USER’S MANUAL C-16 EP _ P I N EP_ PIN Address: Reset Sta te : 1F E7 H XXH Each b it of t he exten ded po rt input (EP_ PIN) registe r refle cts the curr ent state of th e correspo ndin g pi n, reg a rdl e s s of the p in c on fig ura ti on . 7 0 — — — — PIN3 PIN2 PIN1 P IN0 Bit Num ber Bit Mne m oni c F unc tio n 7:4 ...

  • Intel 80C196NU - page 408

    C-17 REGISTERS EP_ REG EP_ REG Address: Reset Sta te : 1F E5 H X0 H Each b it of the e xten ded port data o ut pu t (EP_REG) registe r conta ins dat a t o be driven out b y the corresp ond ing p in. W hen a p in is con figu red a s standa rd I /O (EP _MOD E. x = 0), the result of a CP U write t o EP_R EG is i mme diately visib le on t he pin. Dur i ...

  • Intel 80C196NU - page 409

    8XC1 96NP , 80C196NU USER’S MANUAL C-18 EP A_M ASK EP A _MASK Address: Reset Sta te : 1F9CH AAH The EP A in terr upt mask (EP A_M AS K) regist er e n ab les or d isab les (ma sks) the multiple xed EP A3:0 ove rrun in te rru pts (OVR 3:0). 7 0 — OVR3 — OVR2 — OVR1 — OVR0 Bit Num ber Bit Mne m oni c F unc tio n 7, 5 , 3 , 1 — Re served ; ...

  • Intel 80C196NU - page 410

    C-19 REGISTERS EP A_PEND EP A _PEN D Address: Reset Sta te : 1F 9E H AAH When ha rdwa re d ete cts a pending EP A3:0 overrun inte rrup t (OVR3 :0), i t sets t he co rresp ondin g b it in the EP A interru pt p endin g (EP A _PE ND) re gist er . OVR0 and OVR1 are multip lexe d to share one bit (OVR0 _1) in the INT_ PEND1 re gist er . Simil arly , OVR ...

  • Intel 80C196NU - page 411

    8XC1 96NP , 80C196NU USER’S MANUAL C-20 EP Ax_CON EP A x _CON x = 0– 3 Address: Re set State: Ta b l e C - 8 The EP A con trol (EP A x _CON) registe r s cont rol the f un ctio ns o f thei r a ssigne d capture /com p are cha nnels. Th e registe rs for EP A 0 a ndEP A2 are iden tical. Th e re gisters f or E P A1 a nd EP A 3 h ave an add iti onal ...

  • Intel 80C196NU - page 412

    C-21 REGISTERS EP Ax_CON 5: 4 M1: 0 EP A Mode S e lec t In ca pt ure m ode, sp ecif ie s the type of eve nt t ha t tr igg er s an inp ut cap ture . In compa re mode, specif ie s the action tha t the EP A execu tes when the re fere nce ti mer m at ch es t he eve nt tim e . M1 M 0 Cap ture M ode E vent 00n o c a p t u r e 0 1 cap ture o n fal li ng e ...

  • Intel 80C196NU - page 413

    8XC1 96NP , 80C196NU USER’S MANUAL C-22 EP Ax_CON 1 ROT Rese t Op posi te Ti mer Con tro ls d iffer en t fu ncti on s fo r cap ture a nd com p are mod e s. In Cap ture M ode : 0 = ca uses no actio n 1 = re sets the opposite timer In Com pa re M o de: Sele cts the timer t ha t is t o be rese t if the RT bit is set . 0 = se lects t he re fere nce t ...

  • Intel 80C196NU - page 414

    C-23 REGISTERS EP Ax_CON T able C- 8. EP A x _CON Addresse s and Re set V alues Re gis te r Add res s Rese t Value EP A0_CON 1F80 H 00H EP A1_ CO N 1F 84H 00 00H EP A2_CON 1F88 H 00H EP A3_ CO N 1 F8C H 00 00H ...

  • Intel 80C196NU - page 415

    8XC1 96NP , 80C196NU USER’S MANUAL C-24 EP Ax_TIME EP A x _T IM E x = 0 –3 Address: Reset Sta te : T abl e C- 9 T he EP A ti me ( EP A x _TIM E) reg iste r s are th e event-t im e reg ister s f or the EP A channe ls. In captu re mod e, the value o f th e refere nce time r is cap tured in EP A x _TIM E wh en a n i nput tra nsit io n o ccu rs. Ea ...

  • Intel 80C196NU - page 416

    C-25 REGISTERS INT_M AS K INT _MASK Address: Reset Sta te : 0008H 00 H The interru pt m ask (INT _MASK ) re giste r e nabl es o r d isab les (mas ks) i ndivid ua l int erru pt req u ests. (Th e EI and DI i nstru ct ions en ab le an d disab le se r vicing of a ll ma ska ble inte rrup ts.) INT _M ASK is the l ow by te of th e process o r st a tus w o ...

  • Intel 80C196NU - page 417

    8XC1 96NP , 80C196NU USER’S MANUAL C-26 INT_M AS K 1 INT _MASK1 Address: Reset Sta te : 0013H 00 H The inte rrup t ma sk 1 (INT_ M ASK1 ) r eg ister ena bles o r d isab les (m asks ) indi vidual int erru pt requ ests. (Th e EI a nd DI i n structi on s enab le and disabl e ser vicing o f a ll m as kable interr up ts. ) INT_MASK 1 can be re ad fro ...

  • Intel 80C196NU - page 418

    C-27 REGISTERS INT _PE N D INT _PE ND Address: Reset Sta te : 0009H 00 H When h ardwar e d etects a pe nding int erru pt, i t set s the corr espo ndin g bit in the in terr upt p endi ng (INT _PE ND or INT _PE ND1) re gisters. W he n the vecto r is take n, the har dware cle ars th e pen ding b it. Softwa re ca n gene rat e an interr up t b y setti n ...

  • Intel 80C196NU - page 419

    8XC1 96NP , 80C196NU USER’S MANUAL C-28 INT_P E N D1 INT _PE ND1 Address: Reset Sta te : 0012H 00 H When h ardwar e d etects a pe nding int erru pt, i t set s the corr espo ndin g bit in the in terr upt p endi ng (INT _PE ND or INT _PE ND1) re gisters. W he n the vecto r is take n, the har dware cle ars th e pen ding b it. Softwa re ca n gene rat ...

  • Intel 80C196NU - page 420

    C-29 REGISTERS ONES _RE G ONES_REG Address: Reset Sta te : 02 H FF FF H The two-b yte o nes register (ONE S_RE G) is al ways eq ual to FFF FH. I t is useful as a f ixed source of all ones f or co mpa rison ope rati on s. 15 8 One (h igh b yte) 7 0 On e ( lo w byte ) Bit Num ber F unc tio n 15 : 0 On e The se b its a re al ways eq ual to FFF FH. ...

  • Intel 80C196NU - page 421

    8XC1 96NP , 80C196NU USER’S MANUAL C-30 Px_DIR P x _DIR x = 1– 4 Address: Reset Sta te : T a bl e C -1 0 Each pin o f p o rt x can ope rate i n any o f t he stan d ard I/O mode s of oper ati on: co mp le men tary o utpu t, open -dra in ou tpu t, or hi gh-im ped an ce in put. T he por t x I/O dir ectio n (P x _DIR) re gi ster d eterm ines th e I ...

  • Intel 80C196NU - page 422

    C-31 REGISTERS Px_M ODE P x _MODE x = 1– 4 Add re ss : Rese t St ate: Ta b l e C - 1 1 Each b i t of the po rt x mod e (P x _MODE ) re gist er controls whe ther the cor respo ndin g pi n functio ns a s a stan da rd I /O port pin or a s a s pecia l-f un ct io n signal. 7 0 x = 1– 3 PIN7 PI N 6 P IN5 PIN4 P IN3 PIN 2 PI N1 P IN0 7 0 x = 4 — — ...

  • Intel 80C196NU - page 423

    8XC1 96NP , 80C196NU USER’S MANUAL C-32 Px _P IN P x _PI N x = 1– 4 Add re ss : Rese t St ate: T a b le C -13 Each bit o f t he po rt x pin in put (P x _PI N) registe r refl ects the curren t state of th e corre sp ondi ng p in, reg ard le ss of the pin co nf igura tio n. 7 0 x = 1– 3 PIN7 PIN6 PIN5 PIN4 PIN 3 PIN2 PI N1 P IN0 7 0 x = 4 —? ...

  • Intel 80C196NU - page 424

    C-33 REGISTERS Px_ REG P x _RE G x = 1– 4 Add re ss : Rese t St ate: T a b le C -14 For a n i np ut, set the correspo ndin g port x d ata ouput (P x _RE G) re giste r bit. For an ou tput, wri te th e data t o be d riven out b y each pi n to t he corre spo nd ing bit o f P x _RE G. When a pin is conf igure d as stan dard I/O ( P x _MODE. y = 0), t ...

  • Intel 80C196NU - page 425

    8XC1 96NP , 80C196NU USER’S MANUAL C-34 PS W PSW no direct access The proces sor sta tus wo rd (PSW ) actua lly con sists of two b ytes. Th e hi gh b yte is the sta tus wo rd, which i s describ e d here ; the lo w b yte is th e I NT_ MASK re gi ster . Th e sta tus word con ta ins o ne b it (PSW. 1 ) that glob ally enab les or disabl es servicing ...

  • Intel 80C196NU - page 426

    C-35 REGISTERS PSW 4 V T Overflow-tra p Flag T hi s fla g is s e t whe n t he ove rflo w flag is se t, bu t it is clear ed only by the CLRV T , JVT , an d JNVT instructi ons. Th is a llows te stin g for a p ossib le overfl ow a t the e nd o f a seque n ce of rela ted a rit hmet ic opera ti ons, w hich is gene ral ly more e fficie nt than te sting t ...

  • Intel 80C196NU - page 427

    8XC1 96NP , 80C196NU USER’S MANUAL C-36 PT S SE L PTS SEL Address: Reset Sta te : 0004H 000 0 H The PTS select (PTSSEL) registe r selects e ither a PTS m i crocod e rou tine or a sta ndar d interru pt service ro utin e for ea ch in terru pt re quest. Set ting a bi t selec ts a PTS m icrocod e r outine; clea ring a bit sele cts a s tan dard int er ...

  • Intel 80C196NU - page 428

    C-37 REGISTERS PT SSRV PTS SRV Address: Reset Sta te : 0006H 000 0 H The PTS service (P T SSRV ) register is used by the h ard war e to i ndicat e that the fina l PTS in t erru p t has been serviced by the P TS routi ne. When PT S COUNT reach es zero, har dwa re clear s t he corre- spo ndin g PTSSEL bit and sets the P T SSRV bit, whi ch requests th ...

  • Intel 80C196NU - page 429

    8XC1 96NP , 80C196NU USER’S MANUAL C-38 PWMx _CONTR OL PW M x _CONTROL x = 0 –2 Ad dre ss : Re set S tat e: T abl e C- 15 The PW M co nt rol (PW M x _CONTROL) reg ister d et ermines th e dut y cycle o f the PWM x ch an ne l. A zero loa ded into this regist er causes the PWM to outp ut a low continu ously (0% duty c ycl e). A n FFH in this reg i ...

  • Intel 80C196NU - page 430

    C-39 REGISTERS SBUF_RX SBUF_RX Add ress : Re se t Sta te: 1F B8H 00H The serial port receive buffer (SBUF_RX) registe r conta ins data recei ved fro m the serial port. T h e seri al port recei ver is buffere d a n d can b eg in receivin g a second d ata byt e b ef ore the first byte is read . Data is h el d i n th e receive shift regi st er until t ...

  • Intel 80C196NU - page 431

    8XC1 96NP , 80C196NU USER’S MANUAL C-40 SBUF_T X S BUF_ TX Ad dre ss : Rese t St ate: 1FBAH 00H The seri al port tran smi t b uffe r (S B UF_ TX) r egister contai ns d ata tha t is r ea dy fo r tra n sm issio n. In mo des 1 , 2 , and 3 , wri ting t o SB U F_TX sta rts a tra n smissio n. In m od e 0, wri tin g t o SB UF_ TX sta rts a tran smi ssio ...

  • Intel 80C196NU - page 432

    C-41 REGISTERS SP SP Address: Reset Sta te : 18 H XXXXH The system’s stac k p o inter (SP) c an poin t anywhe re in an i ntern al or exte rnal mem ory page; it m u st be w ord ali gn ed a nd m u st a lwa ys b e i nit ialize d be for e use. The st a ck p o int er is de cre men ted be fore a PUSH and increme n ted after a POP , so the sta ck pointe ...

  • Intel 80C196NU - page 433

    8XC1 96NP , 80C196NU USER’S MANUAL C-42 S P_BA UD SP_ BAU D Address: Reset Sta te : 1F BCH 000 0 H The seria l p ort b au d rate (SP _BA UD) re gi ster se lects t he seri al po rt b aud rat e a n d clo c k source. Th e most-sig ni fica nt bit sel ects th e clo ck sour ce. The l owe r 15 bi ts rep resen t BAUD _V A LUE, an un sign ed inte ger th a ...

  • Intel 80C196NU - page 434

    C-43 REGISTERS SP_BAUD T able C-16. SP_BAUD V alues Wh en Using t h e Int ernal Clock at 25 MHz Bau d Ra te SP _BAUD Reg iste r V a lue (Note 1) % Error Mo de 0 Mo de 1, 2, 3 Mo de 0 Mo de 1 , 2 , 3 9 60 0 85 15 H 8 0A 2H 0 0 .1 5 4 80 0 8A 2BH 8 14 4H 0 0 .1 6 2 40 0 94 57 H 8 28 A H 0 0 120 0 A8 AFH 8 51 5H 0 0 300 (N ote 2) 94 5 7 H (No te 2) 0 ...

  • Intel 80C196NU - page 435

    8XC1 96NP , 80C196NU USER’S MANUAL C-44 S P_CO N SP_CON Address : Re set State: 1 FBBH 00H The se rial p ort control (SP_ CON) reg iste r sel ects th e com m unicat io ns m od e and en able s or d isab le s the recei ver, parity chec king , a nd nine-b it data tra nsmi s sion . F or t he 80C1 96NU, i t a lso en ab les o r disab le s the divid e-b ...

  • Intel 80C196NU - page 436

    C-45 REGISTERS SP _ S T A T U S SP_ ST ATUS Address: Reset Sta te : 1 FB9 H 0B H The se ria l port stat us (SP _ST A T US) re gi ster cont ains bi ts th at indi cate th e sta tu s of the seri al p ort. 7 0 RPE/RB8 RI TI FE TXE OE — — Bit Num ber Bi t Mn em on ic Func tion 7 RP E/RB8 Re ce ive d P arit y Erro r/Re ceived Bi t 8 RPE is set if par ...

  • Intel 80C196NU - page 437

    8XC1 96NP , 80C196NU USER’S MANUAL C-46 T1CONTRO L T1CONTROL Ad dress: Reset Sta te : 1F 90 H 00 H The t imer 1 con trol (T1 CONTROL ) registe r d eterm ines th e clock sou rce, c oun ting dire ctio n, an d count ra te for tim e r 1 . 7 0 CE UD M2 M1 M0 P2 P1 P0 Bit Num ber Bit Mne m oni c F unc tio n 7 CE C ou nter Ena bl e Thi s bit ena bles or ...

  • Intel 80C196NU - page 438

    C-47 REGISTERS T2CONT ROL T2CONTROL Ad dress: Reset Sta te : 1F 94 H 00 H The t imer 2 con trol (T2 CONTROL ) registe r d eterm ines th e clock sou rce, c oun ting dire ctio n, an d count ra te for tim e r 2 . 7 0 CE UD M2 M1 M0 P2 P1 P0 Bit Num ber Bit Mne m oni c F unc tio n 7 CE C ou nter Ena bl e Thi s bit ena bles or di sabl es t he ti mer . F ...

  • Intel 80C196NU - page 439

    8XC1 96NP , 80C196NU USER’S MANUAL C-48 TI ME R x TIM ER x x = 1 –2 Address: R eset Sta te : T a bl e C -17 Th is regi ster cont ains the valu e o f tim er x . Th is re gi ster ca n b e writ ten , all owi ng ti me r x to b e initi alized to a val ue ot he r th an zero . 15 8 Ti m er V a lu e (h ig h byte ) 7 0 T im er V a lue ( l ow by te ) Bit ...

  • Intel 80C196NU - page 440

    C-49 REGISTERS WSR WS R Address: Reset Sta te : 0014H 00 H The win dow selectio n reg iste r (WSR) has two f u ncti ons. One bit enable s and disa bles the bus-h old proto col. The remai ning b its select w indo ws. Windows map sections of RAM i n to the top o f the lower registe r file , i n 32-, 64-, or 128-b yte incre men ts. PUSHA saves t his r ...

  • Intel 80C196NU - page 441

    8XC1 96NP , 80C196NU USER’S MANUAL C-50 WSR BUSCON1 1F4CH 7AH 00ECH 3D H 0 0 CCH 1EH 0 0CCH BUSCON2 1 F54H 7AH 00F4H 3DH 00D4H 1EH 00D4H BUSCON3 1F5CH 7AH 00FCH 3DH 00DCH 1 EH 0 0D CH BUSCON4 1 F64H 7 BH 0 0 E4H 3DH 00E4H 1EH 0 0 E4H BUSCON5 1F6CH 7 BH 00ECH 3DH 0 0 ECH 1EH 00ECH C ON_REG0 1 FB6H 7DH 00F6H 3EH 00F6H 1FH 00 B6H E P_DI R 1FE3 H 7FH ...

  • Intel 80C196NU - page 442

    C-51 REGISTERS WSR P4_ DIR 1FDB H 7EH 00 FB H 3FH 0 0 DBH 1FH 00 DBH P 4_MODE 1 FD9 H 7EH 00F9H 3FH 00D9 H 1FH 00D9H P4_ PIN 1 FDF H 7 EH 0 0 FFH 3FH 00DFH 1 FH 00DFH P4_ REG 1FDDH 7EH 00 FDH 3FH 0 0 DDH 1 FH 00 DDH PWM0_CONTROL 1FB0H 7DH 0 0 F0H 3EH 00F0H 1FH 00B0H PWM1_CONTROL 1FB2H 7DH 0 0 F2H 3EH 00F2H 1FH 00B2H PWM2_CONTROL 1FB4H 7DH 0 0 F4H 3 ...

  • Intel 80C196NU - page 443

    8XC1 96NP , 80C196NU USER’S MANUAL C-52 WSR 1 WS R1 (8 0C1 96 NU ) Address: Reset Sta te : 0015H 00H Wind ow sele ctio n 1 (WSR1 ) registe r selects a 32- o r 64-b yte segm e nt of t h e u pp er re g iste r file or peri phera l S FRs to be wi ndowe d i nto t he mid dle o f th e lower r eg ister file, be low a ny win dow sel ecte d by th e WSR. 7 ...

  • Intel 80C196NU - page 444

    C-53 REGISTERS WSR 1 BUSCON5 1F 6CH 7BH 0 06CH 3DH 00 6CH CON_REG0 1F B6H 7DH 007 6H 3EH 0076H E P _DI R 1 FE3 H 7FH 00 63H 3 FH 0 063H EP_MODE 1FE1H 7FH 006 1H 3FH 0061 H E P _P IN 1 FE 7H 7F H 00 67H 3 FH 0 067H E P _RE G 1 FE5 H 7FH 00 65H 3 FH 0 06 5H EP A_MA SK † 1F9 CH 7C H 00 7CH 3 EH 0 05C H EP A _PEN D 1F 9EH 7CH 007EH 3EH 00 5EH EP A0_C ...

  • Intel 80C196NU - page 445

    8XC1 96NP , 80C196NU USER’S MANUAL C-54 WSR 1 PWM0_CONT R OL 1FB0H 7DH 0070H 3EH 0070 H PWM1_CONT R OL 1FB2H 7DH 0072H 3EH 0072 H PWM2_CONT R OL 1FB4H 7DH 0074H 3EH 0074 H SBUF_RX 1FB8H 7DH 0078H 3EH 00 78H SBUF_TX 1FBAH 7DH 007AH 3EH 00 7AH SP_BAUD 1FBCH 7DH 007CH 3E H 007CH S P _CO N 1FB BH 7 DH 00 7BH 3 EH 0 07BH SP_ST A TUS 1FB9H 7DH 0079H 3E ...

  • Intel 80C196NU - page 446

    C-55 REGISTERS ZERO_REG ZERO_REG Address: Reset Sta te : 00 H 000 0 H The two-b yte zero reg iste r (Z ERO_RE G) is a lwa ys equ al to zero . I t is u sefu l as a fi xed so urce of the con stan t zero for com p ari sons a nd cal cula tion s. 15 8 Z ero (h igh b yt e) 7 0 Zero ( low byte ) Bit Num ber F unc tio n 15 : 0 Z er o Thi s reg iste r is a ...

  • Intel 80C196NU - page 447

    ...

  • Intel 80C196NU - page 448

    Glossary ...

  • Intel 80C196NU - page 449

    ...

  • Intel 80C196NU - page 450

    Gloss ar y-1 GLOS SARY This glossa ry defines acronyms, abbrevi ations, and te rms tha t have spec ial mea ning in this m an- ual. (Chapt er 1 discusse s notational conventi ons and general term inolog y .) 1-Mbyte m ode The address ing mode that a llows c ode to re side anywhere i n the 1-M byte addressing space. 64 -Kbyt e mode The addre ssing mo ...

  • Intel 80C196NU - page 451

    Gloss ar y-2 8XC1 96NP , 80C196NU USER’S MANUAL chip-se lect u nit The inte grat ed module that select s an external memory devi ce during a n ext erna l bus cyc le. cl e ar The “ 0” value of a bit or the act of giving i t a “0” val ue . Se e als o set . deasser t The act of maki ng a si gnal inac tive (dis abled). The polarity (hi gh or ...

  • Intel 80C196NU - page 452

    Gloss ar y-3 GLOSSARY far data Data tha t can be access ed only with extended inst ruc- tions. See a lso near dat a . FE T Fie l d-e ffec t tra ns ist o r . f Lowercas e “f” repres ent s the freq uency of the internal clock. For the 8XC 196NP , f is alw a ys eq ual to F XTAL 1 (the input fre quency on XT AL1). For t he 80C1 96NU, which em ploys ...

  • Intel 80C196NU - page 453

    Gloss ar y-4 8XC1 96NP , 80C196NU USER’S MANUAL ISR See i nte rrupt ser vice r outine . LONG-INTEGER A 32-bit, signed vari able with values from –2 31 throug h +2 31 –1 . LS B Least-si gnific ant bit of a b yte or leas t-sig nificant byte of a word . MAC See multiply- accumulate . maskab le i nterrupts All interrupts exc ept u nimplem ented o ...

  • Intel 80C196NU - page 454

    Gloss ar y-5 GLOSSARY nonvo l atil e m emory Read-only memor y that re tains its contents w hen p owe r i s r em ove d. M a ny M C S ® 96 microcontrol lers are avai lable wit h eithe r maske d ROM , EP R OM , o r OTPRO M . Consult the Aut o motive P r o ducts or Embedde d Mi cr ocontr ollers da tabook to deter m ine which type of memory is ava ila ...

  • Intel 80C196NU - page 455

    Gloss ar y-6 8XC1 96NP , 80C196NU USER’S MANUAL PSW Processor status word. The high byte of the PSW is the sta tus byte, whic h conta ins one bit tha t globa lly enabl es or disa ble s servic i ng of all mas kable interrupts, one bit that enable s or disables the PTS , and six Bool ean fla gs tha t reflect the stat e of the current p rogram. The ...

  • Intel 80C196NU - page 456

    Gloss ar y-7 GLOSSARY r eser ved m emory A memory location t hat is rese rv ed f o r fa c t ory use or for future e xpansi on. Do not use a r ese rved me mory locat ion e xce pt to i nit ia liz e it wi th F F H. sampled inputs All input pi ns, with the exce pti on of RESET#, are sample d inp uts. The input pin is sample d one s tate time before t h ...

  • Intel 80C196NU - page 457

    Gloss ar y-8 8XC1 96NP , 80C196NU USER’S MANUAL speci al-purpose me m ory A partition of memory use d for storing the int err upt ve ct o r s , PTS vec tors , chi p configurat ion byte s, and several res erved loca tions. standard interrupt Any maskabl e in terrupt that i s a ssi g ned t o the interr upt controller for pro cessing by an int err u ...

  • Intel 80C196NU - page 458

    Index ...

  • Intel 80C196NU - page 459

    ...

  • Intel 80C196NU - page 460

    Index -1 #, de fine d, 1- 3, A- 1 1-Mbyte mode, 5- 1 fetching code , 5 -2 3, 5-25 f etching data, 5-2 6 incr ementi n g S P, 5- 11 memor y c onfig uration e xample , 5-31 64-K byte mode, 5-1, 5-5 fetching code , 5 -2 3, 5-25 f etching data, 5-2 6 incr ementi n g S P, 5- 11 memory c onfi g ura t ion example , 5-27, 5- 29 A A15: 0, B- 6 A19:0, 5-1, 1 ...

  • Intel 80C196NU - page 461

    8XC1 96NP , 80C196NU USER ’ S MANUAL Index -2 Baud-rat e genera tor SIO port, 8-8 BAUD_VAL UE, 8-11, C-42 BHE# , 13-3, B-7 during bu s hold, 13-30 See al so wr ite-contr ol s ignal s BIT, defined, 4-2 Bit -test i nstr uct ions, A- 21 Block diagr am address /da ta bus, 7-11 clock c ir cuit ry, 2-7 cor e, 2-3 core and per ipher als, 2-2 E PA, 10- 2 ...

  • Intel 80C196NU - page 462

    Index -3 INDEX CMP ins truct ion, A -3, A- 1 1, A-49, A-53, A -60 CMPB i nstructio n, A-3, A- 1 2, A-50, A-53, A- 60 CMPL ins tructio n, A-2, A- 1 2, A-51, A-53, A- 60 Code e xec ution, 2-4, 2- 5 Code f et ches, 5-25 CompuSer ve forums , 1 -10 Conditional jump i nstr uctions, A- 5 CON_ REG0, C-50, C-53 C ons ta nt s, n e ar , 5- 2 4 CPU, 2-3 CS 5:0 ...

  • Intel 80C196NU - page 463

    8XC1 96NP , 80C196NU USER ’ S MANUAL Index -4 resetting the time rs, 1 0-21, C-22 selecting t he c apture /compare e vent, 10-20, C-21 selecting t he t ime ba se, 10-1 9, C-20 selecting up or down co unting, 1 0- 16, 10 -1 7, C-46, C-4 7 s ign al s, 10- 2 using for PWM , 6-26, 6-32 S ee a lso port 1, port 6, PW M, ti mer/co unters EPA0_CON, C-50, ...

  • Intel 80C196NU - page 464

    Index -5 INDEX device consi der ations, 11-1–11-11 device r e set, 11- 8, 11 -9, 11-10, 11-11 inte rr u pt proc essor , 2- 6, 6-1 minimum confi gurat ion, 1 1- 1 NMI cons ider ations, 6- 6 noise protec tion, 11 -4 reset inst ruc ti on, 4-14 SIO port c onside rations, 8- 6 HLDA# , 13-4, 13-30, B-8 HLDEN bit, 5-1 4, 13-32 Hold latency, See bus- hol ...

  • Intel 80C196NU - page 465

    8XC1 96NP , 80C196NU USER ’ S MANUAL Index -6 JNC instruc tion, A-2, A-5, A-24, A-51, A-58, A-66 JNE instr uct ion, A- 2, A- 5, A-24, A-5 1, A-58, A- 66 JNH instruc tion, A-2, A-5, A-25, A-51, A- 5 8, A-66 JNST instruct ion, A-2, A-5, A-25, A-5 1, A-58, A-66 JNV instruc tion, A-2, A-5, A-25, A-51, A- 5 8, A-66 JNVT instruc tion, A-2, A-5, A-26, A ...

  • Intel 80C196NU - page 466

    Index -7 INDEX map, A- 2 reserve d, A-3, A-52 Operand type s, See dat a types Operands, a ddre ssi ng, 4-12 Op era ting mod es, 2-12 S ee a lso 1-Mbyte mode, 64-Kbyte m ode OR i nstructio n, A-2, A- 3 3, A- 49, A-54, A- 6 1 ORB ins tructio n, A-2, A- 3 3, A- 49, A-54, A- 6 1 Osc il lat or and powerdown mode, 12-7 exte r nal cryst al, 11-6 on-chip, ...

  • Intel 80C196NU - page 467

    8XC1 96NP , 80C196NU USER ’ S MANUAL Index -8 Power consumptio n, re ducing, 2-12, 12-7 Powerdown mode, 2-12, 12- 7–12-12 circ uitr y, e xte rna l, 12-1 1 controlli ng, 13-15 disabli ng, 12-6, 12-7 ena bling, 1 2-7 enter i ng, 12-6, 1 2-7 exit ing, 1 2-8, 12-11 with EXT I NT, 12-8– 12-12 with RES ET#, 12 - 8 Pre fetch q ueue, 2- 5, 5 -23 Prio ...

  • Intel 80C196NU - page 468

    Index -9 INDEX S ee a lso windows Regis te r R AM and idle mode, 12 - 5 and powerdown mode, 12-7 Regis ter s ACC_ 0 x , 3-4 ACC_ STAT, 3-5 al l oc at i n g, 4- 12 EPA_MAS K, 10- 3 EPA_PEND, 10-3 EP_DIR, 7-1 2, 7-14, 7- 16, 7-17 EP_MODE, 7-12, 7-14, 7-16, 7-17, 7-18 EP_PIN, 7-12, 7-14, 7-16, 7-1 7 EP_REG, 7-12, 7-16, 7-17, 7-18 consider at ions, 7-1 ...

  • Intel 80C196NU - page 469

    8XC1 96NP , 80C196NU USER ’ S MANUAL Index -10 S e ri al I/O p ort ‚ See SIO port Set , de fined, 1- 3 SETC inst ruc tion, A-3, A-36, A-52, A- 59, A-67 SF Rs and i dl e mode, 12 - 5 and powerdown mode, 12-7 CPU, 5-1 2 tabl e of, 5 -12 pe r ip he r al , 5- 7 and windows, 5-13 table of, 5-8 reserve d, 4-1 2, 5-9 with i n direct or i ndexe d opera ...

  • Intel 80C196NU - page 470

    Index-11 INDEX T1DIR, 10-2, B- 11 T2CLK, 10-2, B-11 T2CONTROL, C-51, C-54 T2DIR, 10-2, B- 11 Technic a l supp or t, 1-1 1 Terminology , 1-3 TIJMP i nstructi on, A- 2, A- 4 4, A-51, A-57, A- 64 Timer/ counte r s, 2-11, 10-5, 10- 6 and PWM, 10-12, 10-13, 10 -1 4, 10 - 15 c a scading , 10-6 configur in g pins, 10-2 count rat e, 10-6 resol ution, 10- 6 ...

  • Intel 80C196NU - page 471

    8XC1 96NP , 80C196NU USER ’ S MANUAL Index -12 and SIO baud ra t e, 8-12, 8-1 3 hardwa re co nnections, 11-6, 11- 7 XTAL2 , 11-2, B-12 hardwa re co nnections, 11-6, 11- 7 Y y , def ine d, 1- 4 Z Zero (Z) fl ag, A-4, A- 5, A- 22, A-23, A-24, A- 25, C-34 ...

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