-
Intel 80386 - page 1
...
-
Intel 80386 - page 2
inter Introduction to the 80386 ~ncluding the 80386 Data Sheet April 1986 ...
-
Intel 80386 - page 3
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. Contact your local sales office to obtai ...
-
Intel 80386 - page 4
TABLE OF CONTENTS BOOK I CHAPTER 1 HIGHLIGHTS 1.1 32-bit Architectu re .............................................................. 1-1 1.2 High-performance Implementation ............................................... 1-1 1.3 Virtual Memory Support ........................................................ 1~3 1.4 Configurable Protection ........ ...
-
Intel 80386 - page 5
3.4 Protection ................................................................. 3-10 3.4.1 Privilege ................................................................ 3-10 3.4.2 Privileged Instructions .................................................... 3-12 3.4.3 Segment Protection ...................................................... 3-12 3.4.4 ...
-
Intel 80386 - page 6
Chapter 1 Highlights 1 ...
-
Intel 80386 - page 7
...
-
Intel 80386 - page 8
CHAPTER 1 HIGHLIGHTS The 80386 is a high performance 32-bit micropro- cessor designed to drive the most advanced computer-based applications of today and tomor- row. CAE( CAD workstations, high resolution graphics, publishing, and office and factory automation are representative of today's appli- cations that are well-served by the 80386. Tomo ...
-
Intel 80386 - page 9
HIGHLIGHTS porating all of these, the 80386 delivers the highest perfonnance of any currently available microprocessor. The 80386 is implemented in Intel's CHMOS III, a semiconductor process that combines the high frequency of HMOS with the modest power requirements of CMOS. Using 1.5 microngeome- tries and two metal layers, the 80386 packs ov ...
-
Intel 80386 - page 10
HIGHLIGHTS computes the address and definition of the next bus cycle during the current bus cycle. Address pipelining exposes this advance information to the memory subsystem, allowing one memory bank to decode the next bus cycle while another bank is responding to the current cycle. 1.3 Virtual Memory Support Virtual memory enables the maximum siz ...
-
Intel 80386 - page 11
HIGHTLIGTHS protection system and can therefore be used by all applications, including those that will run in production without protection. More impor- tantly, they provide the ability to set data breakpoints in addition to the more familiar instruction breakpoints. The 80386 monitors all four current break point addresses simultaneously without s ...
-
Intel 80386 - page 12
Chapter 2 2 Application Architecture ...
-
Intel 80386 - page 13
...
-
Intel 80386 - page 14
CHAPTER 2 APPLICATION ARCHITECTURE The 80386 provides the assembly language appli- cation programmer or compiler writer with an extensive set of 32-bit resources. The chapter describes these resources in three sections: I) registers, 2) memory and logical addressing, and 3) data types and instructions. 2.1 Registers Computers, including the 80386, ...
-
Intel 80386 - page 15
APPLICATION ARCHITECTURE prevent application programs from inadvertently altering the system flags. The 80386 Instruction Pointer, called EIP, is 32 bits wide. The Instruction Pointer controls instruc- tion fetching (including prefetching) and the processor automatically increments it after exe- cuting an instruction. Interrupts, exceptions, and co ...
-
Intel 80386 - page 16
APPLICATION ARCHITECTURE REGISTER STACK 79 78 64 63 ± EXPONENT SIGNIFICAND CONTROL REGISTER STATUS REGISTER Figure 2-3. Numeric Coprocessor Registers 2.2 Memory and logical Addressing 80386 application programs use logical addresses to specify the locations of operands in a 4- gigabyte physical address space. The processor automatically translates ...
-
Intel 80386 - page 17
APPLICATION ARCHITECTURE logical address names a segment's descriptor. Conceptually, the processor determines a seg- ment's address by using the selector as an index into a descriptor table maintained by the operating system. Adding the offset part of the logical address to the base address obtained from the segment's descriptor prod ...
-
Intel 80386 - page 18
APPLICATION ARCHITECTURE current stack segment (defined by the SS register). To improve instruction encoding efficiency, most instructions do not name segment registers. Instead, the 80386 automatically selects a segment register based on the instruction being executed. For example, a Jump instruction implicitly refers to the CS register and a Push ...
-
Intel 80386 - page 19
APPLICATION ARCHITECTURE Any or all of the base, index, and displacement variables can be used to compute an offset. The base and index variables are the values of general registers, while the displacement value is con- tained in the instruction. Any general register can serve as a base or index register. The value in the index register can be scal ...
-
Intel 80386 - page 20
APPLICATION ARCHITECTURE Table 2-1. Principal Data Types and Instructions Type Integer, Ordinal Size 8, 16,32 bits Unpacked I digit Decimal Packed 2 digits Decimal Instructions Move, Exchange, Translate, Test, Compare, Convert, Shift, Double Shift, Rotate, Not, Negate, And, Or, Exclusive Or, Add, Subtract, Multiply, Divide, Increment, Decrement, Co ...
-
Intel 80386 - page 21
APPLICATION ARCHITECTURE registers, respectively. The Push instruction pushes a dword onto the stack and the Pop instruction pops the top d word from the stack into a register or to memory. Push All pushes the general registers onto the stack and Pop All does the reverse. The Enter and Leave instructions are provided for block-structured high-level ...
-
Intel 80386 - page 22
APPLICATION ARCHITECTURE transfered to any point in a segment. (The selector part of the far pointer replaces the value in the CS register while the offset part replaces the value in EIP) A full set of condi- tional Jump instructions, which branch based on the value of a status flag, is also available; these instructions can also transfer to locati ...
-
Intel 80386 - page 23
APPLICATION ARCHITECTURE implements a "top of loop" test that allows the loop to be executed zero times. 2.3.3.3 Miscellaneous Instructions The 80386 Bound instruction can be used to verify that an array subscript is within the bounds of the array. There are instructions for setting and clearing flags, and for loading and storing the stat ...
-
Intel 80386 - page 24
Chapter 3 System Architecture 3 ...
-
Intel 80386 - page 25
...
-
Intel 80386 - page 26
CHAPTER 3 SYSTEM ARCHITECTURE The purpose of a system architecture is to support operating systems, but operating systems are quite diverse in their needs. In response, the 80386 provides an array of resources that operat- ing system designers and implementors can selectively employ. In effect, the 80386 system architecture can be configured to fit ...
-
Intel 80386 - page 27
SYSTEM ARCHITECTURE program is a text that describes an algorithm, and a task is one execution (performance) ofthat algorithm. The programs that tasks execute are designed as though they were to run on dedicated processors sharing a common memory; that is, except ror occasional pauses to communicate or synchronize with other tasks, a task theoretic ...
-
Intel 80386 - page 28
SYSTEM ARCHITECTURE the new task's Instruction Pointer. To later resume execution of the old task, the operating system issues a Jump TSS to the old task's TSS; execution of the old task then continues with the instruction following the Jump TSS that sus- pended the task. The task switch described here takes 17 microseconds (16 M Hz., no ...
-
Intel 80386 - page 29
SYSTEM ARCHITECTURE A selector is an index into a segment descriptor table; that is, it is a segment number. Each entry in a segment descriptor table contains the base address of a segment. The processor adds the offset to the segment's base address to produce a 32-bit linear address. If paging is not enabled, the processor considers the linea ...
-
Intel 80386 - page 30
SYSTEM ARCHITECTURE address space to be a single entity shared by all tasks and the operating system itself; in other words, a single segment is shared system-wide. At the other extreme, a system might map every data structure and procedure into a different segment, making a task's logical address space consist of dozens or hundreds of address ...
-
Intel 80386 - page 31
SYSTEM ARCHITECTURE operating system must insert a descriptor for the segment into the G DT or into the task's LDT. In protected systems, the G DT and LDT can be made privileged structures so that only the operating system can modify them. As its name implies, all tasks share the Global Descriptor Table; operating systems normally place descri ...
-
Intel 80386 - page 32
SYSTEM ARCHITECTURE and segment registers) from the new task's TSS on task switches. Tasks may share a segment in three ways (see Figure 3-5): 1. A segment whose descriptor is in the GDT is shared by all tasks. 2. Tasks that share an LOT share the segments described in the LOT; this approach is appropriate for closely cooperating tasks. 3. Des ...
-
Intel 80386 - page 33
SYSTEM ARCHITECTURE of reference principle suggests that the new entry is likely to be used again in the near future. While enabling paging does not increase address translation time, it does make instruction execu- tion time vary slightly, due to the occasional TLB misses. By disabling paging, real-time systems can eliminate this potential respons ...
-
Intel 80386 - page 34
SYSTEM ARCHITECTURE infrequently, a virtual memory system will per- form nearly as well as one with far more memory at a fraction of the cost. The key architectural features needed to efficiently support virtual memory are: o A bit for each segment or page that tells the processor (or memory management unit) if the segment or page is "present& ...
-
Intel 80386 - page 35
SYSTEM ARCHITECTURE When, in the course of translating a logical address, the processor produces a linear address that refers to a page table entry whose Present bit is reset, the processor raises an exception called a page fault. Exceptions are covered later in this chapter, but the basic consequence of a page fault is the invocation by the proces ...
-
Intel 80386 - page 36
SYSTEM ARCHITECTURE may take one of four values. Privilege level 0 is the most-privileged level and privilege level 3 is the least-privileged level. Figure 3-8 shows how the 80386 privilege levels can be used to establish different protection policies. An unprotected system can be imple- mented by simply placing all procedures in a segment (or segm ...
-
Intel 80386 - page 37
SYSTEM ARCHITECTURE 3.4.2 Privileged Instructions In addition to defining which segments and pages it can use, a task's privilege level defines the instructions it can execute. The 80386 has a number of instructions whose execution must be tightly controlled to prevent serious system disruption. All of the instructions that load new values int ...
-
Intel 80386 - page 38
SYSTEM ARCHITECTURE 3.4.4 Page Protection Systems that do not make extensive use of segments can instead protect pages. (Page protec- tion can also be applied to sections of large segments.) Like a descriptor, a page table entry has a set of protection attributes; the 80386 checks every reference to the page for confor- mance to these attributes. A ...
-
Intel 80386 - page 39
SYSTEM ARCHITECTURE allowed to call the service procedures but not the kernel; service procedures can, however, call the kernel. Accordingly, the operating system has provided a gate for the service procedures; the privilege level of this gate is 3 so user code can call through it. By assigning the kernel gate privilege level I , the operating syst ...
-
Intel 80386 - page 40
SYSTEM ARCHITECTURE Thble 3-1., Exceptions ID Description 0 Divide Error Debug Exception 3 Software Breakpoint 4 Overflow 5 Array Bound Check 6 Invalid Opcode 7 Coprocessor Not Present 8 Double Fault 10 Invalid TSS 11 Segment Fault 12 Stack Under/ Overflow 13 General Protection Violation 14 Page Fault 16 Coprocessor Error 3.6.1. Interrupt Descripto ...
-
Intel 80386 - page 41
SYSTEM ARCHITECTURE Ideally, interrupts should be handled by tasks, not procedures, because an interrupt is generally unrelated to the task it interrupts. Moreover, an interrupt handler should have its own resources (for example, its own stack) rather than "inherit- ing" those of whatever task happens to be running when the interrupt occu ...
-
Intel 80386 - page 42
SYSTEM ARCHITECTURE Memory-mapped devices can be protected by the standard 80386 segment and page protection mechanisms. In addition to its memory address space, the 80386 has a 64 kilobyte I/O address space. Devices mapped into this space are manipulated with the Input, Output, Input String, and Output String instructions. The first two instructio ...
-
Intel 80386 - page 43
...
-
Intel 80386 - page 44
Chapter 4 4 Architectural Compatibility ...
-
Intel 80386 - page 45
...
-
Intel 80386 - page 46
CHAPTER 4 ARCHITECTURAL COMPATIBILITY The 80386 is compatible at the object code level with both the 80286 and the 8086. While it is possible to use the 80386 simply as a fast 80286 or a very fast 8086, its compatibility facilities are substantially more versatile. The 80386 can execute 80286 and 80386 programs concurrently, and, using the 80386&ap ...
-
Intel 80386 - page 47
ARCHITECTURAL COMPATIBILITY Because the address space of an 8086 is one megabyte, the logical addresses generated by a Virtual 86 Mode task fall into the first megabyte of the 80386 linear address space. Multiple Virtual 86 Mode tasks could interfere with each other, since they would all share the low megabyte of the linear address space. An operat ...
-
Intel 80386 - page 48
ARCHITECTURAL COMPATIBILITY (::: V Figure 4-1. Trapping Virtual 86111ode System Calls 4-3 ...
-
Intel 80386 - page 49
...
-
Intel 80386 - page 50
Chapter 5 5 Hardware Implementation ...
-
Intel 80386 - page 51
...
-
Intel 80386 - page 52
CHAPTER 5 HARDWARE IMPLEMENTATION The 80386 architecture described in the previous chapters is implemented in over 275,000 transis- tors using Intel's CHMOS III process. This chapter looks briefly inside the 80386 chip, and in more detail at the signals by which the 80386 and other components communicate. 5.1 Internal Design Figure 5-1 is an a ...
-
Intel 80386 - page 53
HARDWARE IMPLEMENTATION Pipelining instruction fetch, decode, and execu- tion units on a single chip is not unusual in modern microprocessors. On the other hand, placing the memory management unit (MMU) in the on-chip pipeline is quite unusual. Incor- porating the MMU on the processor chip im- proves the speed of addresss translation by reducing si ...
-
Intel 80386 - page 54
HARDWARE IMPLEMENTATION pass through the page unit unaltered. When paging is enabled, the page unit translates linear addresses to physical addresses, and verifies that accesses are consistent with page attributes. The page unit includes a 32-entry translation look- aside buffer (TLB) that caches the translation information for the most recently us ...
-
Intel 80386 - page 55
HARDWARE IMPLEMENTATION and device drivers, the effective width of the data bus can be dynamically switched between 16 and 32 bits. This topic is discussed in a subsequent section. The 80386 instruction set supports 8-, 16-, and 32-bit transfers. The address bus is organized to directly specify the data bytes that are active in a given bus cycle. T ...
-
Intel 80386 - page 56
HARDWARE IMPLEMENTATION to provide two-clock access to high-speed cache and local memories of any size. (The effectiveness of a memory cache depends on its size relative to the reference patterns of the application.) The latter gives lower-speed memory systems more time to respond to a bus cycle while still keeping the 80386 running at maximum spee ...
-
Intel 80386 - page 57
HARDWARE IMPLEMENTATION cannot respond in two clocks can stretch the bus cycle by holding READY inactive, that is, by inserting wait states into the cycle. When running back-to-back 32-bit bus cycles, the 80386's maxi- mum bus bandwidth is 32 megabytes per second at 16 MHz or 25 megabytes per second at 12.5 MHz. Due to its internal pipelining, ...
-
Intel 80386 - page 58
HARDWARE IMPLEMENTATION 5.2.5 Dynamic Bus Sizing In addition to controlling the timing of bus cycle definitions, the memory (and 1/0) subsystem can also dynamically control the effective size of the data bus. Dynamic bus sizing permits: I. Arbitrary combinations of 16- and 32-bit memory subsystems; software can make 32- bit transfers without regard ...
-
Intel 80386 - page 59
HARDWARE IMPLEMENTATION WAIT instruction, which suspends the 80386 until BUSY goes inactive. The coprocessor asserts ERROR when it encounters an exception that should be handled by operating system software; the 80386 in turn invokes the numeric CLK2 [ BEO, BEl [ ADDRESS AND [ DEFINITION ADS [ BS16 [ READY [ 00-015 [ 016-031 [ exception handler by ...
-
Intel 80386 - page 60
Chapter 6 80386 Data Sheet 6 ...
-
Intel 80386 - page 61
...
-
Intel 80386 - page 62
80386 HIGH PERFORMANCE 32-BIT MICROPROCESSOR WITH ~NTEGRATED MEMORY MANAGEMENT l!II Flexible 32-Bit Microprocessor - 8, 16, 32-Bit Data Types - 8 General Purpose 32-Bit Registers [;'] Very Large Address Space - 4 Gigabyte Physical - 64 Terabyte Virtual - 4 Gigabyte Maximum Segment Size o Integrated Memory Management Unit - Virtual Memory Suppo ...
-
Intel 80386 - page 63
UPDATE NOTICE This 80386 databook, version -002, contains updates and improvements to the first version. A revision sum- mary is listed here for your convenience. The sections that are new or significantly revised are: 2.9.6 Interrupt Priorities 2.9.7 2.9.8 2.11.2 2.12 3.1 4.4.3.3 Fig.4-15a Fig.4-15b 4.6.4 4.6.6 5.6 5.7 5.8 5.8.1 Table 6-3 7.4 7.5 ...
-
Intel 80386 - page 64
1. TABLE OF CONTENTS ........................................................ 3-5 2. BASE ARCHITECTURE .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
-
Intel 80386 - page 65
3. REAL MODE ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 31 3.1 Real Mode Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 31 3.2 Memory Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
-
Intel 80386 - page 66
4. PROTECTED MODE ARCHITECTURE (Continued) 4.6 Virtual 8086 Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55 4.6.1 Executing 8086 Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55 4.6.2 Virtual 8086 Mode Addressing Mechanism . . . . . . ...
-
Intel 80386 - page 67
5. FUNCTIONAL DATA (Continued) 5.4.3.4 Pipe lined Address ............................................... 80 5.4.3.5 Initiating and Maintaining Pipelined Address. . . . . . . . . . . . . . . . . . . . . . . .. 82 5.4.3.6 Pipelined Address with Dynamic Data Bus Sizing. . . . . . . . . . . . . . . . . . . .. 84 5.4.4 Interrupt Acknowledge (INTA) Cycl ...
-
Intel 80386 - page 68
80386 2. BASE ARCHITECTURE 2.1 INTRODUCTION The B03B6 consists of a central processing unit, a memory management unit and a bus interface. The central processing unit consists of the execu- tion unit and instruction unit. The execution unit con- tains the eight 32-bit general purpose registers which are used for both address calculation, data opera ...
-
Intel 80386 - page 69
inter 80386 GENERAL DATA AND ADDRESS REGISTERS 31 16 15 0 AX EAX BX EBX CX ECX DX EDX SI ESI DI EDI BP EBP SP ESP SEGMENT SELECTOR REGISTERS 15 0 CS CODE SS STACK DS } DATA ES FS GS INSTRUCTION POINTER AND FLAGS REGISTER 31 16 15 0 I I IP I EIP FLAGS : EFLAGS Figure 2-1. 80386 Base Architecture Registers The selectors are also task-specific, so the ...
-
Intel 80386 - page 70
inter 80386 FLAGS 3 3 2 2 2 2 2 2 2 222 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 432 1 0 9 8 7 6 5 4 3 2 0 9 8 7 6 5 432 1 0 EFLAGS RESERVED FOR INTEL VIRTUAL MODE---------' RESUME FLAG -:;:;.:======::::'-.J NESTED TASK FLAG I/O PRIVILEGE LEVEL----------' OVERFLOW--------------' DIRECTION FLAG"7===========:::::::~ INTERRUPT ENABLE 2 ...
-
Intel 80386 - page 71
inter 80386 OF (Overflow Flag, bit 11) OF is set if the operation resulted in a signed overflow. Signed overflow occurs when the operation resulted in carry/borrow into the sign bit (high-order bit) of the result but did not result in a carry/borrow out of the high- order bit, or vice-versa. For 8/16/32 bit oper- ations, OF is set according to over ...
-
Intel 80386 - page 72
80386 cal space of the machine, 4 Gbytes (2 32 bytes). In Real Address Mode, the maximum segment size is fixed at 64 Kbytes (2 16 bytes). The six segments addressable at any given moment are defined by the segment registers CS, SS, OS, ES, FS and GS. The selector in CS indicates the current code segment; the selector in SS indicates the current sta ...
-
Intel 80386 - page 73
inter 80386 TS (Task Switched, bit 3) TS is automatically set whenever a task switch operation is performed. If TS is set, a coproces- sor ESCape opcode will cause a Coprocessor Not Available trap (exception 7). The trap han- dier typically saves the 80287/80387 context belonging to a previous task, loads the 80287/80387 state belonging to the curr ...
-
Intel 80386 - page 74
80386 SYSTEM ADDRESS REGISTERS 47 32-BITLINEARBASEADDRESS 1615 LIMIT 0 ~~~:I I I SYSTEM SEGMENT REGISTERS DESCRIPTOR REGISTERS (AUTOMATICALLY LOADED) ~5 ( 32-BIT LINEAR BASE ADDRESS 32-BIT SEGMENT LIMIT ATTRIBUTES I " II TR SELECTOR LDTR SELECTOR Figure 2-7. System Address and System Segment Registers LDTR and TR These registers hold the 16-b ...
-
Intel 80386 - page 75
inter 80386 Table 2-1. Register Usage Use in Use in Use in Register Real Mode Protected Mode Virtual 8086 Mode Load Store Load Store Load Store General Registers Yes Yes Yes Yes Yes Yes Segment Registers Yes Yes Yes Yes Yes Yes Flag Register Yes Yes Yes Yes IOPL IOPL' Control Registers Yes Yes PL = 0 PL = 0 No Yes GDTR Yes Yes PL = 0 Yes No Ye ...
-
Intel 80386 - page 76
80386 2.4.2 80386 Instructions Table 2-2b Arithmetic Instructions Table 2-2a Data Transfer ADDITION GENERAL PURPOSE ADD Add operands MOV Move operand ADC Add with carry PUSH Push operand onto stack INC Increment operand by 1 POP Pop operand off stack AAA ASCII adjust for addition PUSHA Push all registers on stack DAA Decimal adjust for addition POP ...
-
Intel 80386 - page 77
infef 80386 Table 2-2d Logical Instructions (Continued) Table 2-2f. Program Control Instructions SHIFTS (Continued) SHL/SHR Shift logical left or right UNCONDITIONAL TRANSFERS SAL/SAR Shift arithmetic left or right CALL Call procedure/task SHLD/ RET Return from procedure SHRD Double shift left or right JMP Jump ROTATES ITERATION CONTROLS ROL/ROR Ro ...
-
Intel 80386 - page 78
80386 2.5 ADDRESSING MODES 2.5.1 Addressing Modes Overview The 80386 provides a total of 11 addressing modes for instructions to specify operands. The addressing modes are optimized to allow the efficient execution of high level languages such as C and FORTRAN, and they cover the vast majority of data references needed by high-level languages. 2.5. ...
-
Intel 80386 - page 79
inter 80386 SEGMENT REGISTER .--------~ BASE REGISTER SS GS FS ES DS + !+- ____ -I DISPLACEMENT (IN INSTRUCTION) EFFECTIVE ADDR ESS LINEAR / SEGMENT LIMIT DESCRIPTOR REGISTERS ADDRESS ACCESS RIGHTS CS LIMIT • TARGET ADDRESS SELECTED SEGMENT BASE ADDRESS ------~ SEGMENT BASE ADDRESS 231630-51 Figure 2-9. Addressing Mode Calculations 2.5.4 Differen ...
-
Intel 80386 - page 80
80386 Table 2-3. BASE and INDEX Registers for 16- and 32-Bit Addresses 16·Bit Addressing 32-Bit Addressing BASE REGISTER BX,BP INDEX REGISTER SI,DI SCALE FACTOR none DISPLACEMENT 0,8, 16 bits The OPERAND LENGTH and Address Length Pre- fixes can be applied separately or in combination to any instruction. The Address Length Prefix does not allow add ...
-
Intel 80386 - page 81
infef 7 0 SIGN ED rrrrrrrrl BYTE~ SIGN BIT.JL--) MAGNITUDE 7 0 U NSIGN ED fT"1T""'1 BYTE L....:.-....J L--...J MAGNITUDE +1 0 1514 87 0 s~~~g 11II Iii iii i i II iii SIGN BIT.J ... IL_M_S_B ___ ...1 MAGNITUDE +1 0 15 0 UNS~~~g II iii iii Iii iii iii i I MAGNITUDE +3 +2 +1 0 31 1615 0 80386 +N 7 0 BINARY fT"1T""&ap ...
-
Intel 80386 - page 82
80386 2.7 MEMORY ORGANIZATION 2.7.1 Introduction ~emory on the 80386 is divided up into 8-bit quanti- ties (bytes), 16-bit quantities (words), and 32-bit quantities (dwords). Words are stored in two consec- utive bytes in memory with the low-order byte at the lowest address, the high order byte at the high ad- dress. Dwords are stored in four conse ...
-
Intel 80386 - page 83
80386 2.7.3 Segment Register Usage The main data structure used to organize memory is the segment. On the 386, segments are variable sized blocks of linear addresses which have certain attributes associated with them. There are two main types of segments: code and data, the segments are of variable size and can be as small as 1 byte or as large as ...
-
Intel 80386 - page 84
80386 The 1/0 ports are accessed via the IN and OUT 1/0 instructions, with the port address supplied as an immediate 8-bit constant in the instruction or in the OX register. All 8- and 16-bit port addresses are zero extended on the upper address lines. The 1/0 in- structions cause the M/IO# pin to be driven low. 1/0 port addresses 00F8H through OOF ...
-
Intel 80386 - page 85
infef 80386 Table 2-5. Interrupt Vector Assignments Instruction Which Return Address Interrupt Points to Function Can Cause Type Number Faulting Exception Instruction Divide Error 0 DIV,IDIV YES FAULT Debug Exception 1 any instruction YES TRAP' NMllnterrupt 2 INT 2 orNMI NO NMI One Byte Interrupt 3 INT NO TRAP Interrupt on Overflow 4 INTO NO T ...
-
Intel 80386 - page 86
80386 the processor to execute the interrupt service rou- tine pointed to by the nth vector in the interrupt ta- ble. A special case of the two byte software interrupt INT n is the one byte INT 3, or breakpoint interrupt. By inserting this one byte instruction in a program, the user can set breakpoints in his program as a debug- ging tool. A final ...
-
Intel 80386 - page 87
80386 2.9.7 Instruction Restart The 80386 fully supports restarting all instructions after faults. If an exception is detected in the instruc- tion to be executed (exception categories 4 through 10 in Table 2-6c), the 80386 invokes the appropriate exception service routine. The 80386 is in a state that permits restart of the instruction, for all ca ...
-
Intel 80386 - page 88
80386 2.11 TESTABILITY 2.11.1 Self-Test The 80386 has the capability to perform a self-test. The self-test checks the function of all of the Control ROM and most of the non-random logic of the part. Approximately one-half of the 80386 can be tested during self-test. Self-Test is initiated on the 80386 when the RESET pin transitions from HIGH to LOW ...
-
Intel 80386 - page 89
80386 31 12 11 0 LINEAR ADDRESS V 0 0 u u w w 0 01 0 0 C # # # TR6 PHYSICAL ADDRESS 0 0 0 0 0 0 0 P REP 0 0 L TR? NOTE: [£] indicates Intel reserved: Do not define; SEE SECTION 2.3.10 Figure 2-12. Test Registers 2.12.1 Breakpoint Instruction A single·byte-opcode breakpoint instruction is avail- able for use by software debuggers. The breakpoint o ...
-
Intel 80386 - page 90
80386 31 16 15 0 BREAKPOINT 0 LINEAR ADDRESS ORO BREAKPOINT 1 LINEAR ADDRESS DR1 BREAKPOINT 2 LINEAR ADDRESS DR2 BREAKPOINT 3 LINEAR ADDRESS DR3 Intel reserved. Do not define. DR4 Intel reserved. Do not define. DR5 0 B B B o 0 o 0 o 0 o 0 o B B B B DR6 T S 0 3 210 LEN I ~ I W I LEN I R I w I LEN I R I w I LEN I R I w 0 o G o 0 OG L G L G L G L G L ...
-
Intel 80386 - page 91
80386 RWi (memory access qualifier bits) A 2-bit RW field exists for each of the four break- points. The 2-bit RW field specifies the type of usage which must occur in order to activate the associated breakpoint. RW Usage Encoding Causing Breakpoint 00 Instruction execution only 01 Data writes only 10 Undefined-do not use this encoding 11 Data read ...
-
Intel 80386 - page 92
80386 the processor during a task switch, to avoid spurious exceptions in the new task. Note that the break- points must be re-enabled under software control. All 80386 Gi bits are unaffected during a task switch. The Gi bits support breakpoints that are active in all tasks executing in the system. 2.12.3.3 DEBUG STATUS REGISTER (DR6) A Debug Statu ...
-
Intel 80386 - page 93
inter 80386 20 o MAX LIMIT FIXED AT 64K IN REAL MODE 1 64K L-_---1 - - - - ~J_----+_--'-j ~ SELECTED SEGMENT SEGMENT BASE 231630-54 Figure 3-1. Real Address Mode Addressing purpose of Real Mode is to set up the processor for Protected Mode Operation. The LOCK prefix on the 80386, even in Real Mode, is more restrictive than on the 80286. This i ...
-
Intel 80386 - page 94
80386 3.3 RESERVED LOCATIONS There are two fixed areas in memory which are re- served in Real address mode: system initialization area and the interrupt table area. Locations OOOOOH through 003FFH are reserved for interrupt vectors. Each one of the 256 possible interrupts has a 4-byte jump vector reserved for it. Locations FFFFFFFOH through FFFFFFF ...
-
Intel 80386 - page 95
80386 4.2 ADDRESSING MECHANISM Like Real Mode, Protected Mode uses two compo- nents to form the logical address, a 16-bit selector is used to determine the linear base address of a seg- ment, the base address is added to a 32-bit effective address to form a 32-bit linear address. The linear address is then either used as the 32-bit physical address ...
-
Intel 80386 - page 96
80386 4.3 SEGMENTATION 4.3.1 Segmentation Introduction Segmentation is one method of memory manage- ment. Segmentation provides the basis for protec- tion. Segments are used to encapsulate regions of memory which have common attributes. For exam- ple, all of the code of a given program could be con- tained in a segment, or an operating system table ...
-
Intel 80386 - page 97
inter 80386 4.3.3.2 GLOBAL DESCRIPTOR TABLE The Global Descriptor Table (GDT) contains de- scriptors which are possibly available to all of the tasks in a system. The GDT can contain any type of segment descriptor except for descriptors which are used for servicing interrupts (Le. interrupt and trap descriptors). Every 3B6 system contains a GDT. Ge ...
-
Intel 80386 - page 98
80386 attributes include the 32-bit base linear address of the segment, the 20-bit length and granularity of the segment, the protection level, read, write or execute privileges, the default size of the operands (16-bit or 32-bit), and the type of segment. All of the attribute information about a segment is contained in 12 bits in the segment descr ...
-
Intel 80386 - page 99
80386 Code and data segments have several descriptor fields in common. The accessed A bit is set whenev- er the processor accesses a descriptor. The A bit is used by operating systems to keep usage statistics on a given segment. The G bit, or granularity bit, specifies if a segment length is byte-granular or page-granular. 80386 segments can be one ...
-
Intel 80386 - page 100
80386 4.3.4.4 LDT DESCRIPTORS (S = 0, TYPE = 2) LDT descriptors (S = 0 TYPE = 2) contain informa- tion about Local Descriptor Tables. LDTs contain a table of segment descriptors, unique to a particular task. Since the instruction to load the LDTR is only available at privilege level 0, the DPL field is ignored. LDT descriptors are only allowed in t ...
-
Intel 80386 - page 101
intJ 80386 Task gates are used to switch tasks. Task gates may only refer to a task state segment (see section 4.4.6 Task Switching) therefore only the destination selector portion of a task gate descriptor is used, and the destination offset is ignored. Exception 13 is generated when a destination selec- tor does not refer to a correct descriptor ...
-
Intel 80386 - page 102
SEGMENT REGISTER 80386 SELECTOR 15 4 3 2 1 a I 0 I 0 ---- a I a 11 11 nil R~L I . INDEX N 6 5 4 ~ 2 1 a . TABLE INDICATOR TI-1 A DESC~IPTOR LOCAL DESCRIPTOR TABLE N DESCRIPTOR NUMBER 6 5 4 3 2 1 0 TI-a! NULL GLOBAL DESCRIPTOR TABLE Figure 4·10. El(smple Descriptor Selection 41 231630-59 ...
-
Intel 80386 - page 103
inter 80386 4.3.4.10 SEGMENT DESCRIPTOR REGISTER SETTINGS The contents of the segment descriptor cache vary depending on the mode the 80386 is operating in. When operating in Real Address Mode, the segment base, limit, and other attributes within the segment cache registers are defined as shown in Figure 4-11 . For compatiblity with the 8086 archit ...
-
Intel 80386 - page 104
80386 When operating in Protected Mode, the segment base, limit, and other attributes within the segment cache registers are defined as shown in Figure 4-12. In Protected Mode, each of these fields are defined according to the contents of the segment descriptor indexed by the selector value loaded into the seg- ment register. SEGMENT DESCRIPTOR CAC ...
-
Intel 80386 - page 105
inter 80386 When operating in a Virtual 8086 Mode within the Protected Mode, the segment base, limit, and other attributes within the segment cache registers are de- fined as shown in Figure 4-13. For compatibility with the 8086 architecture, the base is set to sixteen times the current selector value, the limit is fixed at OOOOFFFFH, and the attri ...
-
Intel 80386 - page 106
80386 4.4 PROTECTION 4.4.1 Protection Concepts CPU ENFORCED SOFTWARE INTERFACES HIGH SPEED OPERATING SYSTEM INTERFACE APPLICATIONS 231630-63 Figure 4-14. Four-Level Hierachical Protection The 80386 has four levels of protection which are optimized to support the needs of a mUlti-tasking op- erating system to isolate and protect user programs from e ...
-
Intel 80386 - page 107
inter 80386 Virtual 8086 Mode, refer to section 4.6.4 Protection and 110 Permission Bitmap. The 110 privilege level (IOPL) also affects whether several other instructions can be executed or cause an exception 13 fault instead. These instructions are called "IOPL·sensitive" instructions and they are CLI and STI. (Note that the LOCK prefix ...
-
Intel 80386 - page 108
80386 Table 4-3. Descriptor Types Used for Control Transfer Control Transfer Types Intersegment within the same privilege level Intersegment to the same or higher privilege level Interrupt within task may change CPL Intersegment to a lower privilege level (changes task CPL) Task Switch 'NT (Nested Task bit of flag register) ~ 0 "NT (Neste ...
-
Intel 80386 - page 109
p-------------. , ACCESS I TSS , , f+ - , RIGHTS LIMIT , , , , , , BASE f+ , , , , : 31 PROGRAM 0' , , INVISIBLE , 10 ______ ------_. TASK REGISTER TR SELECTOR ~ 15 0 Type ~ 9: Available 386 TSS, Type ~ B. Busy 386 TSS 31 80386 31 16 0000000000000000 I ESPO 0000000000000000 I ESPI 15 BACK LINK SSO ~ 4 8 C 10 TSS BASE STACKS FOR 00000000000000 ...
-
Intel 80386 - page 110
80386 31 63 95 127 31302928272625242322212019181716151413121110987654321 0 1 1 1 1 0 1 1 0 o 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 o 0 0 0 0 0 1 1 0 0 1 0 0 0 1 1 1 1 0 0 1 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 o 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 000 o 0 0 0 0 o 0 0 0 0 0 0 0 0 0 0 0 0 0 o 0 0 1 1 1 1 1 1 1 1 &apos ...
-
Intel 80386 - page 111
infef 80386 15 0 BACK LINK SELECTOR TO TSS SP FOR CPL 0 SS FOR CPL 0 SP FOR CPL 1 SS FOR CPL 1 SP FOR CPL 2 SS FOR CPL 2 IP (ENTRY POINT) FLAGS AX CX OX BX SP BP SI 01 ES SELECTOR CS SELECTOR SS SELECTOR OS SELECTOR TASK'S LOT SELECTOR AVAILABLE , o 2 4 6 INITIAL STACKS 8 FOR CPL 0,1,2 A C E 10 12 14 16 18 CURRENT 1A TASK IC STATE IE 20 22 24 ...
-
Intel 80386 - page 112
80386 31 a FFFFFFFF 15 a RESET ROUTINES SS §ITI tFtFtFto INITIALIZATION GS §ITI ROUTINES FS §ITI ES §ITI USER MEMORY CS GDTR """'" 1 DATA DESCRIPTOR 00000110 CODE DESCRIPTOR 00000 108 GDT NULL SELECTOR 00000100 INTERRUPT t DESCRIPTORS (32) IDT t 00000000 231630-66 Figure 4-17. Simple Protected System DATA DESCRIPTOR 2 C ...
-
Intel 80386 - page 113
inter 80386 ging divides programs into multiple uniform size pages. Pages bear no direct relation to the logical structure of a program. While segment selectors can be considered the logical "name" of a program module or data structure, a page most likely corre- sponds to only a portion of a module or data struc- ture. By taking advantage ...
-
Intel 80386 - page 114
80386 31 12 11 10 9 8 7 6 5 4 3 2 1 0 OS U R PAGE FRAME ADDRESS 31 .. 12 RESERVED 0 0 D A 0 0 - - P S W Figure 4-21. Page Table Entry (Points to Page) 4.5.2.4 PAGE TABLES Each Page Table is 4K bytes and holds up to 1024 Page Table Entries. Page Table Entries contain the starting address of the page frame and statistical information about the page ( ...
-
Intel 80386 - page 115
80386 4.5.4 Translation Lookaside Buffer The 80386 paging hardware is designed to support demand paged virtual memory systems. However, performance would degrade substantially if the proc- essor was required to access two levels of tables for every memory reference. To solve this problem, the 80386 keeps a cache of the most recently accessed pages, ...
-
Intel 80386 - page 116
80386 U/S W/R Access Type 0 0 Supervisor' Read 0 1 Supervisor Write 1 0 User Read 1 1 User Write 'Descriptor table access will fault with u/s 0, even lithe program is executing at level 3. Figure 4-238. Type of Access Causing Page Fault 4.5.6 Operating System Responsibilities The 80386 takes care of the page address transla- tion process, ...
-
Intel 80386 - page 117
inter 80386 VIRTUAL MODE 8086 TASK PAGE DIRECTORY ROOT VIRTUAL MODE 8086 TASK 8086 OS EMPTY TASK 1 PAGE TABLE PAGE DIRECTORY TASK 1 PHYSICAL MEMORY ........... ~~~ 02000000(H) ~I TASK 1 WI!! MEMORY I777l TASK 2 rtfLA MEMORY OOOOOOOO(H) 111 8086 OS MEMORY ~ 80386 OS ~ MEMORY 231630-69 Figure 4-24. Virtual 8086 Environment Memory Management Figure 4? ...
-
Intel 80386 - page 118
80386 In Virtual 8086 Mode, a slightly different set of in- structions are made 10PL-sensitive. The following in- structions are 10PL-sensitive in Virtual 8086 Mode: INT n; STI; PUSHF; eLI; POPF; IRET The PUSHF, POPF, and IRET instructions are 10PL- sensitive in Virtual 8086 Mode only. This provision allows the IF flag (interrupt enable flag) to be ...
-
Intel 80386 - page 119
intJ 80386 essor is executing in Protected Mode. That is, one way to enter Virtual 8086 mode is to switch to a task with a 386 TSS that has a 1 in the VM bit in the EFLAGS image. The other way is to execute a 32-bit IRET instruction at privilege level 0, where the stack has a 1 in the VM bit in the EFLAGS image. POPF does not affect the VM bit, eve ...
-
Intel 80386 - page 120
80386 PRIVILEGE LEVEL 0 (HIGHEST) PRIVILEGE LEVEL 3 F=--.J 8086 Application makes ··Open File Call" -> causes General Protection Fault (Arrow #1) (LOWEST) Virtual 8086 Monitor intercepts call. Calls 386 as (Arrow # 2) 386 as opens file returns control to 8086 as (Arrow # 3) 8086 as returns control to application. (Arrow #4) Transparent to ...
-
Intel 80386 - page 121
intJ 80386 5. FUNCTIONAL DATA 5.1 INTRODUCTION The 80386 features a straightforward functional in- terface to the external hardware. The 80386 has separate, parallel buses for data and address. The data bus is 32-bits in width, and bidirectional. The address bus outputs 32-bit address values in the most directly usable form for the high-speed local ...
-
Intel 80386 - page 122
80386 2X CLOCK [ 32-BIT[DO_D31 DATA BUS [ CONTROL BUS{ ARBITRATION INTERRUPTS { CLK2 ~ < DATA BUS ~ v ADS# R~~~: ~ 80386 PROCESSOR HOLD ~ HLDA INTR t> NMI t> RESET t> ADDRESS BUS BE3# BE2# BE1# BEO# W/R# D/C# M/IO# LOCK# PEREQ I~ BUSY# ~ ERROR# Vee <l GND <l t v A2-A31 1 BYTE ENABLES 32-BIT ADDRESS } COPROCESSOR SIGNALLING } POWE ...
-
Intel 80386 - page 123
80386 The Byte Enable outputs, BEO#-BE3#, directly in- dicate which bytes of the 32-bit data bus are in- volved with the current transfer. This is most conve- nient for external hardware. BEO# applies to 00-07 BEl # applies to 08-015 BE2# applies to 016-023 BE3# applies to 024-031 The number of Byte Enables asserted indicates the physical size of t ...
-
Intel 80386 - page 124
80386 Table 5-2 Bus Cycle Definition MIIO# D/C# W/R# Bus Cycle Type Locked? Low Low Low INTERRUPT ACKNOWLEDGE Yes Low Low High does not occur Low High Low 1/0 DATA READ No Low High High I/O DATA WRITE No High Low Low MEMORY CODE READ No High Low High HALT: SHUTDOWN: No Address = 2 Address = 0 (BEO# High (BEO# Low BE1 # High BE1 # High BE2# Low BE2# ...
-
Intel 80386 - page 125
intJ 80386 80386 I/O cycles automatically generated for co- processor communication do not require BS16# be asserted. The coprocessor type, 80287 or 80387, is sensed on the ERROR# input shortly after the faIl- ing edge of RESET. The 80386 transfers only 16-bit quantities between itself and the 80287, but must transfer 32-bit quantities between itse ...
-
Intel 80386 - page 126
80386 5.2.8.4 COPROCESSOR ERROR (ERROR#) This input signal indicates that the previous coproc- essor instruction generated a coprocessor error of a type not masked by the coprocessor's control regis- ter. This input is automatically sampled by the 80386 when a coprocessor instruction is encountered, and if asserted, the 80386 generates excepti ...
-
Intel 80386 - page 127
80386 5.2.10 Signal Summary Table 5-4 summarizes the characteristics of all 80386 signals. Table 5-4_ 80386 Signal Summary Signal Name Signal Function CLK2 Clock 00-031 Data Bus BEO#-BE3# Byte Enables A2-A31 Address Bus W/R# Write-Read Indication OfC# Data-Control Indication M/IO# Memory-I/O Indication LOCK# Bus Lock Indication ADS# Address Status ...
-
Intel 80386 - page 128
80386 Address bits AO and A1 of the physical operand's base address can be created when necessary (for instance, for Multibus I or Multibus II interface), as a function of the lowest-order asserted Byte Enable. This is shown by Table 5-6. Logic to generate AO and A 1 is given by Figure 5-3. Table 5-5. Byte Enables and Associated Data and Opera ...
-
Intel 80386 - page 129
intJ 80386 rrrrrrrrH ...---.., ~1%. ~~ W/ ~ PHYSICAL MEMORY ~ggggg~~~ I ------:+- COPROCESSOR (NOTE 1) W : (80387 OR 80287) 4GBYTE V@ /NOT / ), I ACCESSIBLE. ~ OOOOrrrrH EJ } ACCESSIBLE 64 kBYTE PROGRAMMED OOOOOOOOH I/O SPACE OOOOOOOOH 1..- __ ...1 231630-5 Physical Memory Space 1/0 Space NOTE: Since A31 is HIGH during automatic communication with ...
-
Intel 80386 - page 130
intef 80386 Effect of asserting B516# during "upper half only" read cycles: Asserting B516# during "upper half only" reads causes the 80386 to read data on the lower 16 bits of the data bus and ignore data on the upper 16 bits of the data bus. Oata that would have been read from 016-031 (as indicated by BE2# and BE3 #) will inst ...
-
Intel 80386 - page 131
intJ 80386 pipelined address with 16-bit memories then BEO # - BE3 # and W IR # are also decoded to determine when BS16# should be asserted. See 5.4.3.7 Maxi- mum Pipelined Address Usage with 16-Bit Bus Size.) A2-A31 are directly usable for addressing 32-bit and 16-bit devices. To address 16-bit devices, A1 and two byte enable signals are also need ...
-
Intel 80386 - page 132
inter 80386 8EO# L H L x Ii L L 8E2# L L x H L H L L ;( L H H x x x L [~ A1 8E3# 8E1# ---- 8EO# L H L 8E1# 231630-8 K-map for A 1 signal (same as Figure 5-3) 8EO# L H L x L L L 8E2# L L x H L H H L ·x L H [~ 8HE 8[3# 8E3# --,,--~ 8E1# x x L x L L H L 8E1# 231630-9 K-map for 16-bit SHE # signal 8EO# L H L x L H L L H L x L 8LE# (OR AO) 8E2# H L L X ...
-
Intel 80386 - page 133
inter 80386 The definition of each bus cycle is given by three definition signals: M/IO#, W/R# and D/C#. At the same time, a valid address is present on the byte enable signals BEO # -BE3 # and other address sig- nals A2-A31. A status signal, ADS#, indicates when the 80386 issues a new bus cycle definition and address. Collectively, the address bus ...
-
Intel 80386 - page 134
80386 The fastest 80386 bus cycle requires only two bus states. For example, three consecutive bus read cy- cles, each consisting of two bus states, are shown by Figure 5-8. The bus states in each cycle are named T1 and T2. Any memory or 1/0 address may be accessed by such a two-state bus cycle, if the external hardware is fast enough. The high-ban ...
-
Intel 80386 - page 135
inter 80386 Pipelined address timing is useful in typical systems having address latches. In those systems, once an address has been latched, pipelined availability of the next address allows decoding circuitry to gener- ate chip selects (and other necessary select signals) in advance, so selected devices are accessed im- mediately when the next cy ...
-
Intel 80386 - page 136
inter 80386 5.4.3 Read and Write Cycles 5.4.3.1 INTRODUCTION Data transfers occur as a result of bus cycles, classi- fied as read or write cycles. During read cycles, data is transferred from an external device to the proces- sor. During write cycles data is transferred in the oth- er direction, from the processor to an external de- vice. Two choic ...
-
Intel 80386 - page 137
,/ / / 80386 At the end of the second bus state within the bus cycle, READY # is sampled. At that time, if external hardware acknowledges the bus cycle by asserting READY #, the bus cycle terminates as shown in Fig- ure 5-11. If READY # is negated as in Figure 5-12, the cycle continues another bus state (a wait state) and READY # is sampled again a ...
-
Intel 80386 - page 138
intJ 80386 HOLD ASSERTED REQUEST PENDING. HOLD NEGATED Bus States: ALWAYS READY# ASSERTED' HOLD NEGATED' REQUEST PENDING READY# NEGATED' NA# NEGATED Tl-first clock of a non-pipelined bus cycle (80386 drives new address and asserts ADS#) T2-subsequent clocks of a bus cycle when NA # has not been sampled asserted in the current bus cyc ...
-
Intel 80386 - page 139
inter 80386 5.4.3.3 NON·PIPELINED ADDRESS WITH DYNAMIC DATA BUS SIZING The physical data bus width for any non-pipelined bus cycle can be either 32-bits or 16-bits. At the beginning of the bus cycle, the processor behaves as if the data bus is 32-bits wide. When the bus cy- cle is acknowledged, by asserting READY # at the end of a T2 state, the mo ...
-
Intel 80386 - page 140
inter IDLE Ti CLK2 [ - M (82384 CLK) [ - V 80386 A TRANSFER REQUIRING TWO CYCLES ON 16-81T DATA BUS CYCLE 1 CYCLE 1 A NON-PIPELINED NON-PIPELINED (READ ----!---READ) PART ONE PART TWO T1 T2 T 2 T I T2 T2 nIL M rm rtJl nIL nIL V V V V V V CYCLE 2 NON-PIPELINED (WRITE) T1 T2 T2 nIL rtJl nIL V V V 8EO #. 8El # [ [ XIXXXXX VALID I I NEGATED DURING i V ...
-
Intel 80386 - page 141
80386 5.4.3.4 PIPELINED ADDRESS Address pipelining is the option of requesting the address and the bus cycle definition of the next, in- ternally pending bus cycle before the current bus cycle is acknowledged with READY # asserted. AD5# is asserted by the 80386 when the next ad- dress is issued. The address pipelining option is con- trolled on a cy ...
-
Intel 80386 - page 142
intJ 80386 IDLE CYCLE 1 NON-PIPELINED (WRITE) CYCLE 2 PIPELINED (READ) CYCLE 3 PIPELINED (WRITE) CYCLE 4 PIPELINED (READ) IDLE Ti n T2 T2P np T2P n P T2P T1P T21 T21 Ti ClK2 [ (82384 ClK) [ BEO #- BD #' [ A2-A31, M/IO#, D/C# W /R # [ 44'..¥-l~.J( ADS# [ BS16 # [ 44~~~...l'-.lI...l>( READY # [ 44~~""''"&ap ...
-
Intel 80386 - page 143
inter 80386 NA#' (PIN 013) D--4 NA# (INTERNAL) 9S16# c:_ ..... ---- 9S16 # (PIN C14) (INTERNAL) 231630-22 Figure 5-18. 80386 Internal Logic on NA# and 8516# The complete bus state transition diagram, including operation with pipelined address is given by 5-20. Note it is a superset of the diagram for non-pipelined address only, and the three a ...
-
Intel 80386 - page 144
inter CLK2 [ (82384 ClK) [ BED # - BE 1 #, [ A2- A31, M/IO#, D/c# W/R# [ ADS# [ 8S16 # [ READY# [ lOCK# [ DO- D31 [ TlP CYCLE 1 PIPELINED (WRITE) T2P T2P ASSERTING NA# MORE THAN ONCE DURING ANY CYCLE HAS NO ADDITIONAL EFFECTS T1P 80386 CYCLE 2 PIPELINED (READ) T2 T2P NA# COULD HAVE BEEN ASSERTED IN Tl P IF DESIRED. ASSERTION NOW IS THE LATEST TIME ...
-
Intel 80386 - page 145
Bus States: RESET ASSERTED 80386 HOLD ASSERTED READY# ASSERTED- HOLD NEGATED- NO REQUEST T1-first clock of a non·pipelined bus cycle (80386 drives new address and asserts ADS #). T2-subsequent clocks of a bus cycle when NA # has not been sampled asserted in the current bus cycle. T21-subsequent clocks of a bus cycle when NA # has been sampled as· ...
-
Intel 80386 - page 146
intJ 80386 quest, and is allowed to drive the next internally pending address onto the bus. Asserting NA # there- fore makes it impossible for the next bus cycle to again access the current address on A2-A31, such as may be required when B8 16 # is asserted by the external hardware. been sampled asserted in the current cycle. If NA# is sampled asse ...
-
Intel 80386 - page 147
inter 80386 Certain types of 16-bit or 8-bit operands require no adjustment for correct transfer on a 16-bit bus. Those are read or write operands using only the low- er half of the data bus, and write operands using only the upper half of the bus since the 80386 simul- taneously duplicates the write data on the lower half of the data bus. For thes ...
-
Intel 80386 - page 148
inter 80386 CYCLE 1 I NON-PIPELINED (WRITE) T1 T2 CYCLE 2 I NON-PIPELINED (HALT) T1 T2 IDLE Ti Ti Ti Ti CLK2 [ (82384 CLK) [ BEO~ BEl" BE3"[ MilO" W/R# 'rr-:":,~:-:--+:,-+---bV'.ml::7o;",,od- 80386 REMAINS HAL TED UNTIL INTR, NMI OR ~"-lo"-..lj'-l"-lo"-~t- RESET IS ASSERTED. I I BE2#, A2- ...
-
Intel 80386 - page 149
intJ 80386 5.4.6 Shutdown Indication Cycle the only signals distinguishing shutdown indication from halt indication. which drives an address of 2. During the shutdown cycle undefined data is driven on 00-031. The shutdown indication cycle must be acknowledged by READY # asserted. The 80386 shuts down as a result of a protection fault while attempti ...
-
Intel 80386 - page 150
80386 5.5 OTHER FUNCTIONAL DESCRIPTIONS 5.5.1 Entering and Exiting Hold Acknowledge The bus hold acknowledge state, Th, is entered in response to the HOLD input being asserted. In the bus hold acknowledge state, the 80386 floats all output or bidirectional signals, except for HLDA. HLDA is asserted as long as the 80386 remains in the bus hold ackno ...
-
Intel 80386 - page 151
inter 80386 NOTE: CLK2[ (82384 ClK) [ HOLD [ HLDA [ BEO#-BE3#, A2-A31, [ M/IO#, D/C#, W /R# ADS# [ T1 CYCLE 1 NON-PIPELINED (READ) T2 T2 NOTE: IF ASSERTING BS 16# REQUIRES A SECOND BUS CYCLE TO BE PERFORMED, THE SECOND CYCLE IS PERFORMED BEFORE HOLD ACKNOWLEDGE HOLD CYCLE 2 ACKNOWLEDGE NON-PIPELINED (WRITE) Th Th T1 T2 VALID 2 OUT 231630-30 HOLD is ...
-
Intel 80386 - page 152
intJ 80386 CLK2[ (82384 CLK) [ HOLD [ HLDA [ 8EO#-8E3#, A2-A31, [ M/IO#, D/c#, W/R# ADS# [ TIP CYCLE 1 PIPELINED (WRITE) T21 T21 HOLD CYCLE 2 ACKNOWLEDGE NON-PIPELINED (READ) Th Th TI T2 NA# [ ..Qja~-4~~~~~~~~~~~~ 231630-31 NOTE: HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold (t23 and t24) require- ments a ...
-
Intel 80386 - page 153
intJ 80386 INTERNAL I----RESET----I---INITIALIZATION-----+l ClK2[ RESET [ (FROM 82384) ClK (INTERNAL) [ (82384ClK) [ 9USY# [ ERROR# [ 9EO#-9E3#. W/R#.M/IO#. [ HlDA ~ 15 ClK2 DURATION IF NOT GOING TO REQUEST SELF-TEST. DURING RESET A2-A31. [ D/C#. lOCK# ~~_~_ DURING RESET ADS#[ ~~~~ DURING RESET CYCLE 1 NON-PIPELINED (READ) T1 T2 NA#[ ~~~~~~~~~~~~I. ...
-
Intel 80386 - page 154
inter 80386 5.8 COPROCESSOR INTERFACING The 80386 provides an automatic interface for the Intel 80287 or 80387 numeric floating-point coproc- essors. The 80287 and 80387 coprocessors use an I/O-mapped interface driven automatically by the 80386 and assisted by three dedicated signals: BUSY #, ERROR #, and PEREa. As the 80386 begins supporting a cop ...
-
Intel 80386 - page 155
inter 80386 ~[Q)W~OO~[g OOOIP@OO~~lf'O@OO 6. MECHANICAL DATA vee and GND connections must be made to multi- ple Vee and Vss (GND) pins. Each Vee and Vss must be connected to the appropriate voltage level. 6.1 INTRODUCTION The circuit board should include Vee and GND planes for power distribution and all Vee and Vss In this section, the physica ...
-
Intel 80386 - page 156
inter 80386 A B c D E F G H K L N p o 0 000 0 0 0 000 0 0 0 vee vss A8 All A14 A15 A16 A17 A20 A21 A23 A26 A27 A30 2 o 0 000 0 0 0 0 000 0 0 2 VSS A5 A7 Al0 A13 VSS vee A18 VSS A22 A24 A29 A31 vee 3 o 0 0 0 0 0 0 0 0 0 0 000 3 A3 A4 A6 A9 A12 VSS vee A19 VSS A25 A28 vee VSS D30 4 000 000 4 Ne Ne A2 vss vee D29 5 000 000 5 vee vss vee METAL LID D31 ...
-
Intel 80386 - page 157
intJ 80386 Table 6-1. 80386 PGA Pinout-Functional Grouping Pin /Signal Pin/ Signal Pin/Signal Pin/Signal N2 A31 M5 031 A1 Vee A2 Vss P1 A30 P3 030 A5 Vee A6 Vss M2 A29 P4 029 A7 Vee A9 Vss L3 A28 M6 028 A10 Vee 81 Vss N1 A27 N5 027 A14 Vee 85 Vss M1 A26 P5 026 C5 Vee 811 Vss K3 A25 N6 025 C12 Vee 814 Vss L2 A24 P7 024 012 Vee C11 Vss L1 A23 N8 023 ...
-
Intel 80386 - page 158
inter 80386 0;- r:- ~ ;;;- N 0;- r:- "' "' '" <J) 0 ... OJ ' '" ... ~ OJ I') OJ .,; .,; C ~ e e c c c C IN #l POSITION 2 3 4 5 6 7 • ®00®00'10000000 ®00®0000000000 o ® ~ 0 0 ® ®'0 0 0 0 ~ 0 0 000 00® ®®0 ®00 0®0 I ®00 0®0 + 00® B -0 0 @ - - - - ® 0 ® 9 10 11 12 13 14 ...
-
Intel 80386 - page 159
inter 6.4 PACKAGE THERMAL SPECIFICATION 80386 to determine whether the 80386 is within specified operating range. The 80386 is specified for operation when case tem- perature is within the range of 0°C-85°C. The case temperature may be measured in any environment, The PGA case temperature should be measured at the center of the top surface opposi ...
-
Intel 80386 - page 160
infef 80386 Table 6-2. Several Socket Options for 132-Pin PGA (Continued) Peel-A-WayTM Mylar and Kapton Socket Terminal Carriers • Low insertion force surface mount CSI32-37TG Low insertion force soldertail CS132-0tTG Low insertion force wire-wrap CS132-02TG (two level) CS132-03TG (three-level) • Low insertion force press-fit CS132-05TG Advance ...
-
Intel 80386 - page 161
inter 80386 7. ELECTRICAL DATA 7.1 INTRODUCTION The following sections describe recommended elec- trical connections for the 80386, and its electrical specifications. 7.2 POWER AND GROUNDING 7.2.1 Power Connections The 80386 is implemented in CHMOS III technology and has modest power requirements. However, its high clock frequency and 72 output buf ...
-
Intel 80386 - page 162
80386 7.3 MAXIMUM RATINGS Table 7-2. Maximum Ratings 80386·12 Parameter 80386·16 Maximum Rating Storage Temperature - 65'C to + 150'C Case Temperature Under Bias -65'Cto +110'C Supply Voltage with Respect to Vss - 0.5V to + 6.5V Voltage on Other Pins -0.5VtoVcc + 0.5V 7.4 D.C. SPECIFICATIONS Table 7-2 is a stress rating only, ...
-
Intel 80386 - page 163
intJ 80386 7.5 A.C. SPECIFICATIONS 7.5.1 A.C. Spec Definitions The A.C. specifications, given in Tables 7-4 and 7-5, consist of output delays, input setup requirements and input hold requirements. All A.C. specifications are relative to the CLK2 rising edge crossing the 2.0V level. A.C. spec measurement is defined by Figure 7-1. In- puts must be dr ...
-
Intel 80386 - page 164
intJ 80386 ~[Q)W~[RI]~~ OOO[f@OOfMl~'TI'O@OO 7.5.2 A.C. Specification Tables Functional Operating Range: Vee = 5V ±5%; TeASE = O°C to 85°C Table 7·4. 80386-16 A.C. Characteristics Symbol Parameter 80386-16 80386-16 Unit Ref. Notes Min Max Figure Operating Frequency 4 16 MHz Half of CLK2 Frequency t1 CLK2 Period 31 125 ns 7-3 t2a CLK2 ...
-
Intel 80386 - page 165
inter 80386 Table 7-4. 80386-16 A.C. Characteristics (Continued) Symbol NOTES: Parameter RESET Hold Time NMI, INTR Setup Time NMI, INTR Hold Time PEREQ,ERROR#,BUSY# Setup Time PEREQ,ERROR#,BUSY# Hold Time 80386-16 80386-16 Min Max 3 15 15 15 9 1. Float condition occurs when maximum output current becomes less than IL tested. 2. These inputs are aI/ ...
-
Intel 80386 - page 166
intJ 80386 ~[Q)W~OO©[g OOOIP@OOIMl~'iiO@OO Table 7-5. 80386-12 A.C. Characteristics (Continued) Symbol Parameter 80386-12 80386-12 Notes Min Max t15 NA# Setup Time 12 t16 NA# Hold Time 22 t17 8S16# Setup Time 14 t1B 8S16# Hold Time 22 t19 REAOY# Setup Time 22 7-4 t20 REAOY# Hold Time 7-4 t21 00-031 Read 7-4 Setup Time t22 00-031 Read 7-4 Hold ...
-
Intel 80386 - page 167
CLK2 [ READY# [ HOLD [ DO-D31 [ (INPUT) BU5Y#. [ ERROR# PEREQ NA# [ B516# [ INTR. [ NMI CLK2 [ 8EO#-8E3#. [ LOCK# W!R#.M!IO#. [ O!C#.AOS# A2-A31 [ 00-031 [ (OUTPUT) HLOA [ 80386 Tx Tx ~2 Figure 7·4. Input Setup and Hold Timing Tx Figure 7·5. Output Valid Delay Timing 106 Tx 231630-40 231630-41 ...
-
Intel 80386 - page 168
inter CLK2 [ BEO#-BE3#. [ LOCK# W/R#.M/IO#. [ D/C#.ADS# A2-A31 [ DO-D31 [ HLDA [ 80386 Th Ti OR T1 @ ALSO APPLIES TO DATA FLOAT WHEN WRITE CYCLE IS FOLLOWED BY READ OR IDLE MAX Figure 7·6. Output Float Delay and HLDA Valid Delay Timing -RESET--I~'----INITIALIZATION SEQUENCE ---- CLK2 [ RESET [ The second internal processor phase following RES ...
-
Intel 80386 - page 169
inter 80386 7.6 DESIGNING FOR ICE-386 USE The 80386 in-circuit emulator product is ICE-386. Because of the high operating frequency of 80386 systems and ICE-386, there is no cable separating the ICE-386 probe module from the target system. The ICE-386 probe module has several electrical and mechanical characteristics that should be taken into consi ...
-
Intel 80386 - page 170
80386 'y 5.100 o o o .800 o o i I f • PIN 1 .150-. - .80 + .68 REF t •. 200 ! 0.188 2 PL 231630-76 Figure 7-9. ICE-3S6 Optional Interface Module Clearance Requirements (inches) COMPONENT SIDE PROCESSOR MODULE PI~ ~, rDl 1: ___ _ o LEVER OF ZIF SOCKET 231630-74 Figure 7-10. Recommended Orientation of Lever-Actuated ZIF Socket for ICE-3S6 Us ...
-
Intel 80386 - page 171
intJ 80386 8. INSTRUCTION SET This section describes the 80386 instruction set. A table lists all instructions along with instruction en- coding diagrams and clock counts. Further details of the instruction encoding are then provided in the fol- lowing sections, which completely describe the en- coding structure and the definition of all fields occ ...
-
Intel 80386 - page 172
80386 a e T bl 8 -1.8 3 6 o 8 I nstructlon S CI et ock C ount S ummary CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Mode or Virtual Mode or Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode GENERAL DATA TRANSFER MOV ~ Move: Register to Register/Memory I 1000100w I mod reg rim 1 2/2 2/2 b h R ...
-
Intel 80386 - page 173
intJ 80386 Table 8·1. 80386 Instruction Set Clock Count Summary (Continued) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected - Mode or Virtual Mode or Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode SEGMENT CONTROL LOS ~ Load Pointer to OS 11000101 mod reg rim! 7 22 b h.i.j LES ~ Load Pointer ...
-
Intel 80386 - page 174
80386 a e - T bl 8 1 80386 I nstructlon et oc S CI kC ount S ummary (C ontlnue d) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Mode or Virtual Mode or Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode ARITHMETIC (Continued) Register from Memory I 00101 DOw ImOdreg r/ml 7 7 b h Memory from Re ...
-
Intel 80386 - page 175
inter 80386 Table 8·1 80386 Instruction Set Clock Count Summary (Continued) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Mode or Virtual Mode or Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode ARITHMETIC (Continued) DIV ~ Divide (Unsigned) Accumulator by Register/Memory I 11 11011 w Imod ...
-
Intel 80386 - page 176
80386 Table 8-1. 80386 Instruction Set Clock Count Summary (Continued) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Mode or Virtual Mcdeor Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode LOGIC (Continued) Register to Memory I OOtOOOOw I mod reg r/ml 7 7 b h Memory to Register I 0010001w I ...
-
Intel 80386 - page 177
inter 80386 Table 8-1. 80386 Instruction Set Cloc k Count S ummary( c ontlnued) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Modear Virtual Modear Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode REPEATED STRING MANIPULATION (Continued) REPNE CMPS ~ Compare String ClkCount (Find Match) I ti ...
-
Intel 80386 - page 178
inter 80386 Table 8-1. 80386 Instruction Set Clock Count Summar (Continued) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Mode or Virtual Mode or Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode CONTROL TRANSFER (Continued) Protected Mode Only (Direct Intersegment) Via Call Gate to Same Priv ...
-
Intel 80386 - page 179
80386 a e - T bl 8 1 80386 I f ns rue Ion e oe S tCI k C oun tS ummary (C r on Inue d) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Mode or Virtual Modecr Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode CONTROL TRANSFER (Continued) RET ~ Return from CALL: Within Segment I 11000011 I 10 + m ...
-
Intel 80386 - page 180
intJ 80386 Table 8-1. 80386 Instruction Set Clock Count Summary (Continued) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Mode or Virtual Mode or Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode CONDITIONAL JUMPS (Continued) JNS ~ Jump on Not Sign 8~Bit Displacement I 01111001 I 8-bil displ ...
-
Intel 80386 - page 181
80386 Table 8-1. 80386 Instruction Set Clock Count Summary (Continued) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Mode or Virtual Mode or Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode CONDITIONAL BYTE SET (Continued) SETNB ~ Set Byte on Not Below/Above or Equal To Register/Memory I 000 ...
-
Intel 80386 - page 182
80386 a e - T bl 8 1 80386 I nstructlon et oc S CI kC oun tS ummaay (C ontmue d) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Mode or Virtual Mode or Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode INTERRUPT INSTRUCTIONS INT ~ Interrupt: Type Specified I 11001101 I type I 37 b Type 3 I 110 ...
-
Intel 80386 - page 183
intJ 80386 T bl a e 8-1. 8 o 61 38 nstructlon et oc S CI kC ount S ummary (C ontlnue d) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Mode or Virtual Mode or Virtual Virtual Address Virtual Addresa 8086 Mode 8086 Mode Mode Mode INTERRUPT INSTRUCTIONS (Continued) BOUND: Via Interrupt or Trap Gate to Same Privileg ...
-
Intel 80386 - page 184
infef 80386 a e T bl 8 -1. 803 86 nstructlon et oc S CI kC ount S ummary (C ontlnue d) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Mode or Virtual Mode or Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode PROCESSOR EXTENSION INSTRUCTIONS Processor Extension Escape 111011 TTT I modLLL rim I ...
-
Intel 80386 - page 185
infef 80386 a e -1. T bl 8 803861 ns rue Ion e oe t" StCI kC ount 5 ummary (C ontlnue d) CLOCK COUNT NOTES Real Real INSTRUCTION FORMAT Address Protected Address Protected Madear Virtual Modear Virtual Virtual Address Virtual Address 8086 Mode 8086 Mode Mode Mode SlOT ~ Store Interrupt Descriptor Table Register I 00001111 I 00000001 ImodOOl rI ...
-
Intel 80386 - page 186
inter 80386 8.2 INSTRUCTION ENCODING 8.2.1 Overview All instruction encodings are subsets of the general instruction format shown in Figure 8-1. Instructions consist of one or two primary opcode bytes, possibly an address specifier consisting of the "mod rim" byte and "scaled index" byte, a displacement if re- quired, and an imm ...
-
Intel 80386 - page 187
80386 8.2.2 32-Bit Extensions of the Instruction Set With the 80386, the 86/186/286 instruction set is extended in two orthogonal directions: 32-bit forms of all 16-bit instructions are added to support the 32- bit data types, and 32-bit addressing modes are made available for all instructions referencing mem- ory. This orthogonal instruction set e ...
-
Intel 80386 - page 188
80386 Register Specified by reg Field During 32-Bit Data Operations Function of w Field reg (whenw = 0) (whenw = 1) 000 AL EAX 001 CL ECX 010 DL EDX 011 BL EBX 100 AH ESP 101 CH EBP 110 DH ESI 111 BH EDI 8.2.3.3 ENCODING OF THE SEGMENT REGISTER (sreg) FIELD The sreg field in certain instructions is a 2-bit field allowing one of the four 80286 segme ...
-
Intel 80386 - page 189
infef 80386 Encoding of 16·bit Address Mode with "mod rIm" Byte mod rIm Effective Address mod rIm Effective Address 00000 OS:[BX+Sil 10000 OS:[BX+SI +d16) 00001 OS:[BX+Oil 10001 OS:[BX + 01 + d16) 00010 SS:[BP+Sil 10010 SS:[BP+SI+d16) 00011 SS:[BP+Oil 10011 SS:[BP+ 01 + d16) 00100 OS:[Sil 10100 OS: [SI + d16) 00101 OS:[Oil 10101 OS: [01 ...
-
Intel 80386 - page 190
inter 80386 Encoding of 32-bit Address Mode with "mod rIm" byte (no "s-i-b" byte present): mod rIm Effective Address mod rIm Effective Address 00000 OS: [EAX) 10000 OS:[EAX+d32) 00001 OS: [ECX) 10001 OS: [ECX + d32) 00010 OS:[EOX) 10010 OS: [EOX + d32) 00011 OS:[EBX) 10011 OS: [EBX + d32) 00100 s-i-b is present 10100 s-i-b is pr ...
-
Intel 80386 - page 191
intJ 80386 Encoding of 32-bit Address Mode ("mod rim" byte and "s-i-b" byte present): mod base Effective Address 00000 OS: [EAX + (scaled index)] 00001 OS: [ECX + (scaled index)] 00010 OS: [EOX + (scaled index)] 00011 OS: [ESX + (scaled index)] 00100 SS: [ESP + (scaled index)] 00101 OS: [d32 + (scaled index)] 00110 OS:[ESI + (sc ...
-
Intel 80386 - page 192
80386 8.2.3.5 ENCODING OF OPERATION DIRECTION (d) FIELD In many two·operand instructions the d field is pres· ent to indicate which operand is considered the source and which is the destination. d Direction of Operation 0 Register/Memory <- - Register "reg" Field Indicates Source Operand; "mod r/m" or "mod ss index bas ...
-
Intel 80386 - page 193
ALABAMA Intel Corp 5015 Bradford Drive SUite 2 Huntsville 35805 Tel (205) 830-4010 ARIZONA Intel Corp 11225 N 28th Drive SUile 2140 PhoeniX 85029 Tel (602) 869-4980 Intel Corp 1161 N. EI Dorado Place SUlle 301 Tucson 85715 Tel. (602) 299-6815 CALIFORNIA Intel Corp 21515 Vanowen Street SUite 116 Canoga Park 91303 Tel' (818) 704·8500 Inlel Corp ...
-
Intel 80386 - page 194
UNITED STATES Intel Corporation 3065 Bowers Avenue Santa Clara, CA 95051 JAPAN Intel Japan K.K. 5,6 Tokodai Toyosato,machi Tsukuba,gun, Ibaraki,ken 300,26 Japan FRANCE Intel Paris 1 Rue Edison, BP 303 78054 Saint,Quentin en Yvelines France UNITED KINGDOM Intel Corporation (U.K.) Ltd. Piper's Way Swindon Wiltshire, England SN~ 1RJ WEST GERMANY ...
Do you have a question concerning Intel 80386?
Use the form below
If you did not solve your problem by using a manual Intel 80386, ask a question using the form below. If a user had a similar problem with Intel 80386 it is likely that he will want to share the way to solve it.