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Manual Xilinx 1000BASE-X

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  • Xilinx 1000BASE-X - page 1

    R LogiCORE™ IP Ethernet 1000B ASE-X PCS/PMA or SGMII v9.1 User Guide UG155 Mar ch 24, 2008 ...

  • Xilinx 1000BASE-X - page 2

    www .xilinx.com Ethernet 1000B ASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Xilinx is disclosing this Specification to you solely f or use in the de v elopment of designs to o perate on Xili nx FPGAs. Except as stated herein, none of the Specification ma y be copied, repr o duced, distributed, re published, do wnloaded, displa y ed, posted, or ...

  • Xilinx 1000BASE-X - page 3

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com UG155 March 24, 2008 Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx 1000BASE-X - page 4

    w ww .xilinx.com Ethernet 1000B ASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 R Implement the Ethernet 1000BAS E-X PCS/PM A or SGMII Core in Your Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Chapter 5: Using the C lient-side GMII Data Path Designing with the Client-side ...

  • Xilinx 1000BASE-X - page 5

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com UG155 March 24, 2008 R Virtex-5 LXT and SXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Virtex-5 FXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 13 Chapter 9: C ...

  • Xilinx 1000BASE-X - page 6

    w ww .xilinx.com Ethernet 1000B ASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 R Virtex-5 Ro cketIO GTX T ransceivers for SGMII or Dynamic Standards Switching Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Ten-Bit Interface Constraints . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx 1000BASE-X - page 7

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com UG155 March 24, 2008 R Appendix B: Core Latency Core Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Latency for 1000BASE-X PCS with TBI . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx 1000BASE-X - page 8

    w ww .xilinx.com Ethernet 1000B ASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 R ...

  • Xilinx 1000BASE-X - page 9

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com UG155 March 24, 2008 Chapter 2: Core Architecture Figure 2-1: Functional Block Diagram Using RocketIO Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 2-2: Functional Block Diagram with a Ten-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx 1000BASE-X - page 10

    w ww .xilinx.com Ethernet 1000B ASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 R Chapter 6: The Ten-Bit In terface Figure 6-1: Ten-Bit Interface Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 6-2: Ten-Bit-Interface Receiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx 1000BASE-X - page 11

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com UG155 March 24, 2008 R Chapter 11: Dynamic Switching of 1000BASE-X and SGMII Standards Figure 11-1: Typical Application for Dynamic Sw itching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Chapter 12: Constraining the Core Figure 12-1: Local Clock Place and Route ...

  • Xilinx 1000BASE-X - page 12

    w ww .xilinx.com Ethernet 1000B ASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 R ...

  • Xilinx 1000BASE-X - page 13

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com UG155 March 24, 2008 Chapter 2: Core Architecture Table 2-1: GMII Interface Signal Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 2-2: Other Common S ignals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx 1000BASE-X - page 14

    w ww .xilinx.com Ethernet 1000B ASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 R Table 9-21: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 9-22: SGMII Auto-N egotiation Advertiseme nt (Register 4) . . . . . . . . . . . . . . . . . . 139 Table 9-23: SGMII Auto -Negotiation L ink ...

  • Xilinx 1000BASE-X - page 15

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 17 UG155 March 24, 2008 R Pr eface About This Guide The LogiCORE™ IP Ethernet 1000BASE- X PCS/PMA or SGMII User Guide pr ovides information about generating a Xilinx Ethernet 1000 BASE-X PCS/PMA or SGMII cor e, customizing and simulating the core using th e provided example design, and r ...

  • Xilinx 1000BASE-X - page 16

    18 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Preface: About This Guide R • Chapter 1 1, “Dynamic Switching of 1000BASE-X and SGMII Standards” pr ovides general guidelines for u sing the core to perform dynamic standards switching between 1000BASE-X and SGMII. • Chapter 12, “Constraining the Cor e” d ...

  • Xilinx 1000BASE-X - page 17

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 19 UG155 March 24, 2008 Con ventions R Online Document The following conventions ar e used in this document. Square brackets [ ] An optional entry or parameter . However , in bus specifications, such as bus[7:0] , they a re r equired. ngdbuild [ option_name ] design_name Braces { } A list ...

  • Xilinx 1000BASE-X - page 18

    20 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Preface: About This Guide R ...

  • Xilinx 1000BASE-X - page 19

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 21 UG155 March 24, 2008 R Chapter 1 Intr oduction The Ethernet 1000BASE-X PCS/PMA or SGMII co re is a fully verified so lution that supports V erilog HDL and VHDL. In addition, th e example design provided with the cor e supports both V e rilog and VHDL. This chapter introduces the Etherne ...

  • Xilinx 1000BASE-X - page 20

    22 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 1: Introd uction R Additional Core Resour ces For detailed information and updates ab out the Ethernet 1000BASE-X PCS/PMA or SGMII core, s ee the following documents, located on the Xilinx Ethernet 100BASE-X PCS/PMA produc t page . • Ethernet 1000BASE-X PCS ...

  • Xilinx 1000BASE-X - page 21

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 23 UG155 March 24, 2008 Feedbac k R Document For comments or suggestions about this do cument, please submit a W ebCase from www .support.xilinx.com/ . Be sure to include the following inf ormation: • Document title • Document number • Page number(s) to which your comments r efer • ...

  • Xilinx 1000BASE-X - page 22

    24 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 1: Introd uction R ...

  • Xilinx 1000BASE-X - page 23

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 23 UG155 March 24, 2008 R Chapter 2 Cor e Ar chitectur e This chapter describes the ar chitecture of the Ethernet 1000BASE-X PCS/PMA or SGMII core, i ncluding all interf aces and major functional blocks. System Overview Ether net 1000BASE-X PCS/PMA or SG MII Using A Rock etIO T ransceiv er ...

  • Xilinx 1000BASE-X - page 24

    24 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 2: Core Arch itecture R GMII Block A client-side GMII is provided w ith the core, which can be used as an internal interface for connection to an embedded Media Access Co ntroller (MAC) or other custom logic. Alternatively , the GMII may be routed to devi ce ...

  • Xilinx 1000BASE-X - page 25

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 25 UG155 March 24, 2008 System Over view R Optional PCS Man agement Registers Configuration and status of th e cor e, including access to and from the option al Auto- Negotiation function, uses the 1000BASE- X PCS Management Registers defined in IEEE 802.3 clause 37. These registers are ac ...

  • Xilinx 1000BASE-X - page 26

    26 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 2: Core Arch itecture R 8B/10B Encoder 8B10B encoding, as defined in IEEE 802.3 (T ables 36-1a t o 36-1e and T able 36-2), is implemented in a block SelectRAM™, configur ed as ROM, and used as a large look-up table. 8B/10B Decoder 8B10B decoding, as def ine ...

  • Xilinx 1000BASE-X - page 27

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 27 UG155 March 24, 2008 Core Interfaces R functionality . For more information, see Chapter 3, “Generating and Customizing the Core.” Figure 2- 3: Component Pinout Using Roc ketIO T ransceiv er with PCS Mana gement Registers mdc mdio_in gmii_rxd[7:0] gmii_txd[7:0] gmii_tx_en mgt_rx_res ...

  • Xilinx 1000BASE-X - page 28

    28 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 2: Core Arch itecture R Figur e 2-4 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII cor e using a RocketIO transceiver without the optional PCS Management Registers Figure 2- 4: Component Pinout Using Roc ketIO T ransceiv er without PCS Mana gem ...

  • Xilinx 1000BASE-X - page 29

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 29 UG155 March 24, 2008 Core Interfaces R Figur e 2-5 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core when using the TBI wit h optional PCS Management Regi sters. The signals show n in the Auto- Negotiation box ar e included only when th e core includ es the Auto-Negotia ...

  • Xilinx 1000BASE-X - page 30

    30 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 2: Core Arch itecture R Figur e 2-6 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core when using a TBI without the option al PCS Manage ment Registers. Figure 2- 6: Component Pinout Using T en-Bit Inter face without PCS Mana gement Registers ...

  • Xilinx 1000BASE-X - page 31

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 31 UG155 March 24, 2008 Core Interfaces R Figur e 2-7 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII cor e using the optional dynamic switching logic (betw een 1000BASE-X and SGMII standards). This mode is shown used with a RocketIO transc eiver interface. For mor e informat ...

  • Xilinx 1000BASE-X - page 32

    32 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 2: Core Arch itecture R T able 2- 1: GMII Interface Signal Pin out Signal Direction Description gmii_txd[7:0] 1 1. When the T ransmitter Elastic Buffer is present these signals ar e sync hro nous to gm ii_ tx_c lk. Whe n the T ransmitter Elastic Buffer is omi ...

  • Xilinx 1000BASE-X - page 33

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 33 UG155 March 24, 2008 Core Interfaces R Common Signal Pinout Ta b l e 2 - 2 describes the remai ning signals common to al l parameterizations of the core. T able 2- 2: Other Common Signals Signal Direction Description reset Input Asynchronous r eset for the entire core. Active High. Cloc ...

  • Xilinx 1000BASE-X - page 34

    34 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 2: Core Arch itecture R MDIO Management Interf ace Pinout (Optional) Ta b l e 2 - 3 describes the optional MDIO interface signals of the cor e used to access the PCS Management Registers. These signal s are typi cally connected to the MDIO port of a MAC devic ...

  • Xilinx 1000BASE-X - page 35

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 35 UG155 March 24, 2008 Core Interfaces R Configuration V ector (Optional) Ta b l e 2 - 4 shows the alternative to the option al MDIO Management Interface, the configuration vector . See “Optional Configuration V ector” in Chapter 9 . A uto-Negotiation Signal Pinout Ta b l e 2 - 5 desc ...

  • Xilinx 1000BASE-X - page 36

    36 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 2: Core Arch itecture R Dynamic Switching Signal Pinout Ta b l e 2 - 6 describes the signals pr esent when the optional Dy namic Switching mode (between 1000BASE-X and SGMII standards) is selected. In this case, the MDIO ( Ta b l e 2 - 3 ) and RocketIO transc ...

  • Xilinx 1000BASE-X - page 37

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 37 UG155 March 24, 2008 Core Interfaces R T able 2- 7: Optional Rocket IO T ransceiver Interface Pin out Signal Directio n Descriptio n mgt_rx_r eset 1 1. When the cor e is used wi th a RocketIO transceiver , userclk2 is used a s the 125 MHz reference cloc k for the entire cor e. Output Re ...

  • Xilinx 1000BASE-X - page 38

    38 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 2: Core Arch itecture R 1000BASE-X PCS with TBI Pinout Ta b l e 2 - 8 describes the optional TBI signals, used as an alternative to the RocketIO receiver interface. The appr opriate HDL example design delivered with the cor e connects these signals to IOBs to ...

  • Xilinx 1000BASE-X - page 39

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 39 UG155 March 24, 2008 R Chapter 3 Generating and Customizing the Cor e The Ethernet 1000BASE-X PCS/PMA or SGMII cor e is generated using the CORE Generator . This chapter describes the GUI options used to generate and custom ize the core. GUI Interface Figur e 3-1 displays the Ethernet 1 ...

  • Xilinx 1000BASE-X - page 40

    40 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 3: Generating and Customizing the Core R Select Standard Select fr om the following standards f or the cor e: • 1000BASE-X . 1000BASE-X Physical Coding Sublayer (PCS) functiona lity is designed to the IEEE 802.3 specification. Depending on the choice of phy ...

  • Xilinx 1000BASE-X - page 41

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 41 UG155 March 24, 2008 GUI Interface R Ph ysical Interface Depending on the target ar chitecture, two phys ical interface options are available for the core. • RocketIO . Uses a RocketIO transceiver specific to the selected device family to extend the 1000BASE-X functionality to include ...

  • Xilinx 1000BASE-X - page 42

    42 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 3: Generating and Customizing the Core R This screen lets you select the Receiver E lastic Buffer type to be used with the cor e . Befor e selecting this option, see “Receiver Elastic Buffer Impl ementations” in Chapter 8 . Figure 3-3: SGMII/Dynamic Stand ...

  • Xilinx 1000BASE-X - page 43

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 43 UG155 March 24, 2008 P arameter V alue s in the XCO File R Roc k etIO Tile Configur ation The RocketIO T ile Configuration screen is only displayed if the Rock etIO interface is used with the V irtex-4 or V irtex-5 device families. RocketIO transceivers for V irtex-4 FX and V irt ex-5 d ...

  • Xilinx 1000BASE-X - page 44

    44 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 3: Generating and Customizing the Core R Ta b l e 3 - 1 describes the XCO file para meters, valu es and summarizes the GUI defaults. The following is an example of the CSET parameters in an XCO file: CSET component_name=gig_eth_pcs_pma_ v9_1 CSET standard=100 ...

  • Xilinx 1000BASE-X - page 45

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 45 UG155 March 24, 2008 R Chapter 4 Designing with the Cor e This chapter provides information about creating your own designs using the Ethernet 1000BASE-X PCS/PMA or SGMII core . Design guidelines, as we ll as the variety of implementations presented, are based on the example design deli ...

  • Xilinx 1000BASE-X - page 46

    46 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 4: Designing with the Core R 1000BASE-X Standard Using Roc k etIO T ransceiver Example Design Figur e 4-1 illustrates the example design in 1000B ASE-X mode using the V irtex-II Pro or V irtex-4 MGT , V i rtex-5 GTP or V irtex-5 GTX transceiver . As illustrat ...

  • Xilinx 1000BASE-X - page 47

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 47 UG155 March 24, 2008 Design Ov erview R 1000BASE-X Standard with TBI Example Design Figur e 4-2 illustrates the example desi gn in 1000BASE-X mode using a TBI. As illustrated, the example is split between two hierar chical layers. The block level is desi gned so that it can be instantia ...

  • Xilinx 1000BASE-X - page 48

    48 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 4: Designing with the Core R SGMII Standard Using a Rock etIO T ransceiv er Example Design Figur e 4-3 illustrates the example design in SGMII mod e using the V irtex-II Pro or V irtex- 4 MGT , V irtex-5 GTP or V irtex-5 GTX transceive r . This is also the ex ...

  • Xilinx 1000BASE-X - page 49

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 49 UG155 March 24, 2008 Design Ov erview R SGMII Standard with TBI T ransceiv er Example Design Figur e 4-3 illustrates the example design with the SG MII standar d using a TBI. This is also the example design cr eated when the Dynami c Switching capability between SGMII and 1000BASE-X sta ...

  • Xilinx 1000BASE-X - page 50

    50 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 4: Designing with the Core R Design Guidelines Generate the Core Generate the core using the CORE Generator , as described in Chapter 3, “Generating and Customizing the Cor e.” Examine the Example Design Pro vided with the Core Before implementing the cor ...

  • Xilinx 1000BASE-X - page 51

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 51 UG155 March 24, 2008 Design Guidelines R Write an HDL Application After review ing the example design deliver ed wi th the cor e, write an HDL application that uses single or multiple instances of the bl ock level module for t he Ethernet 1000BA SE-X PCS/PMA or SGMII core. Client-side i ...

  • Xilinx 1000BASE-X - page 52

    52 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 4: Designing with the Core R K eep it Registered T o simplify timing and to i ncrease system pe rformance in an FPGA des ign, keep all inputs and outputs r egistered between the user appl ication and the cor e. All inputs and outputs from the user application ...

  • Xilinx 1000BASE-X - page 53

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 53 UG155 March 24, 2008 R Chapter 5 Using the Client-side GMII Data Path This chapter provides general guideli nes for creating designs using client-side GMII of the Ethernet 1000BASE-X PCS/PMA or SGMII core. Designing with the Client-side GMII f or the 1000BASE-X Standar d It is not withi ...

  • Xilinx 1000BASE-X - page 54

    54 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 5: Using the Cli ent-side GMII Data P a th R Error Propagation A corrupted frame transfer is illustrated in Figure 5-2 . An err or may be injected into the frame by ass erting gmii_tx_er at any point during the gmii_tx_en assertion window . The core ensur es ...

  • Xilinx 1000BASE-X - page 55

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 55 UG155 March 24, 2008 Designing with the Cli ent-side GMII f or the 1000B ASE-X Standar d R Nor mal F rame Reception with Extension Field In accordance with the IEEE 802.3 , clause 36, state machines for the 1000BASE-X PCS, gmii_rx_er may be driven high following reception of the end fra ...

  • Xilinx 1000BASE-X - page 56

    56 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 5: Using the Cli ent-side GMII Data P a th R F alse Ca rrier Figur e 5-6 illustrates the GMII signaling for a False Carrier condition. False Carrier is asserted by the cor e in response to certai n error conditions, such as a frame with a corrupted start code ...

  • Xilinx 1000BASE-X - page 57

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 57 UG155 March 24, 2008 Designing with the Cli ent-side GMII f or the 1000B ASE-X Standar d R Bits[4:2]: Code Group Reception Indicators These signals indicate the r eception of part icular types of group, as defined below . Figur e 5-7 illustrates the timing of these signals, showing that ...

  • Xilinx 1000BASE-X - page 58

    58 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 5: Using the Cli ent-side GMII Data P a th R be included in the frame supplied to the core . The RocketIO transceiver will r eplace these four bytes with the calculated CRC value. GMII Reception The timing of normal inbound frame transfer with RocketIO transc ...

  • Xilinx 1000BASE-X - page 59

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 59 UG155 March 24, 2008 Designing with Client -side GMII for the SGMII Standa r d R Designing with Client-side GMII f or the SGMII Standard Ov er vie w When the core is generated for the SGMII standa r d, changes are made to the core that affect the PCS Management Registers and th e Auto-N ...

  • Xilinx 1000BASE-X - page 60

    60 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 5: Using the Cli ent-side GMII Data P a th R 10 Megabit per Second F rame T ransmission The operation of the core r emains unchanged. It is the responsibility of the client logic (for example, an Ethernet MAC), to enter data at the corre ct rate. When operati ...

  • Xilinx 1000BASE-X - page 61

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 61 UG155 March 24, 2008 Using the GMII as an Internal Connection R 10 Megabit per Second F r ame Reception The operation of the core remains unchanged. When operating at a speed of 10 Mbps, every byte of the MAC frame (fr om destination address to the frame check sequence field, inclusive) ...

  • Xilinx 1000BASE-X - page 62

    62 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 5: Using the Cli ent-side GMII Data P a th R Vir tex-II Pro and Virtex-II De vices Figure 5- 14 illustrates how to create an external GMII transmitter in a V irtex-II family device. The signal names and l ogic shown on th e figur e exactly match those deliver ...

  • Xilinx 1000BASE-X - page 63

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 63 UG155 March 24, 2008 Implementing Ext ernal GMII R Spar tan-3, Spar tan-3E and Spar tan-3A De vices The logic described pr eviously for V irtex-II and V irtex-II Pro devices does not meet the input setup and hold r equirements for GMII wi th Spartan-3, Spartan-3E, and Spartan-3A devices ...

  • Xilinx 1000BASE-X - page 64

    64 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 5: Using the Cli ent-side GMII Data P a th R Vir tex-4 De vices The logic described pr eviously for V irtex-II and V irtex-II Pro devices does not meet the input setup and hold r equireme nts for GMII with V irtex-4 devices. T wo possible solutions are: 1. A ...

  • Xilinx 1000BASE-X - page 65

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 65 UG155 March 24, 2008 Implementing Ext ernal GMII R Vir tex-5 De vices Figure 5- 17 illustrates how to create an external GMII transmitter in a V irtex-5 family device. The signal names and l ogic shown on th e figur e exactly match those delivered with the example design. The IODELA Y e ...

  • Xilinx 1000BASE-X - page 66

    66 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 5: Using the Cli ent-side GMII Data P a th R GMII Receiv er Logic Figure 5- 18 illustrates an external GMII r eceiver created in a V irtex-II family device. The signal names and logic shown in the figur e exactly match those de livered with the example design ...

  • Xilinx 1000BASE-X - page 67

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 67 UG155 March 24, 2008 Implementing Ext ernal GMII R Figure 5-18 : External GMII Receiver Logic IOB LOGIC OBUFT FDDRRSE OP AD D Q '0' '1' gmii_rxd_obuf[0] OP AD OP AD OP AD OBUFT OBUFT OBUFT D Q D Q D Q D Q gmii_rx_dv_obuf gmii_rx_er_obuf gmii_rxd[0] gmii_rx_dv gmii_rx ...

  • Xilinx 1000BASE-X - page 68

    68 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 5: Using the Cli ent-side GMII Data P a th R ...

  • Xilinx 1000BASE-X - page 69

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 69 UG155 March 24, 2008 R Chapter 6 The T en-Bit Interface This chapter provides general guidelines for creating 1000BASE-X, SGMII or Dynamic Standards S witching designs using the T en-Bit Interface (TBI). An explanation of the TBI logic in all supported device families is provided, as we ...

  • Xilinx 1000BASE-X - page 70

    70 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 6: The T en-Bit Interface R Receiv er Logic Vir tex-II and Virtex-II Pro De vices Figur e 6-2 illustrates an external r eceiver TBI in V irtex-II devices. The signal names and logic displayed precisely match those delivered with the example design when the TB ...

  • Xilinx 1000BASE-X - page 71

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 71 UG155 March 24, 2008 T en-Bit-Interf ace Logic R synchronous to pma_rx_clk0_bufg and pma_rx_clk1_bufg , res pectively . These busses are then immediately register ed insi de the core on their respective clock. Figure 6-2: T en-Bit-I nterface Rece iver Logic component_name _bloc k (Block ...

  • Xilinx 1000BASE-X - page 72

    72 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 6: The T en-Bit Interface R Spar tan-3, Spar tan-3E and Spar tan-3A De vices The logic described pr eviously for V irtex-II and V irtex-II Pro devices does not meet the input setup and hold r equirements for TBI wi th Spartan-3, Spartan-3E and Spartan-3A dev ...

  • Xilinx 1000BASE-X - page 73

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 73 UG155 March 24, 2008 T en-Bit-Interf ace Logic R Vir tex-4 De vices Method 1 The V irtex-4 FPGA logic used by the example de sign deli vered with the core is il lustrated in Figure 6- 4 . This sho ws a V irtex-4 device IDDR primitive used with the DDR_CLK_EDGE attribute set to SAME_EDGE ...

  • Xilinx 1000BASE-X - page 74

    74 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 6: The T en-Bit Interface R Method 2 This logic from method 1 r e lies on pma_rx_clk0 and pma_rx_clk1 being exactly 180 degree s out of phase with each other since the falling e dge of pma_rx_clk0 is used in place of pma_rx_clk1 . See the data sheet for the a ...

  • Xilinx 1000BASE-X - page 75

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 75 UG155 March 24, 2008 T en-Bit-Interf ace Logic R Vir tex-5 De vices Method 1 The V irtex-5 FPGA logic used by the example de sign deli vered with the core is il lustrated in Figure 6- 6 . This sho ws a V irtex-5 device IDDR primitive used with the DDR_CLK_EDGE attribute set to SAME_EDGE ...

  • Xilinx 1000BASE-X - page 76

    76 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 6: The T en-Bit Interface R Method 2 This logic from method 1 r e lies on pma_rx_clk0 and pma_rx_clk1 being exactly 180 degree s out of phase with each ot her because the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1 . See the data sheet for the ...

  • Xilinx 1000BASE-X - page 77

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 77 UG155 March 24, 2008 Cloc k Sharing acr oss Multiple Cores with TBI R Cloc k Sharing acr oss Multiple Cores with TBI Figur e 6-8 illustrates sharing clock resources across multiple instantiations of the core when using the TBI. gtx_clk may be shared between multiple cores, r esulti ng i ...

  • Xilinx 1000BASE-X - page 78

    78 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 6: The T en-Bit Interface R ...

  • Xilinx 1000BASE-X - page 79

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 79 UG155 March 24, 2008 R Chapter 7 1000BASE-X with RocketIO T ransceivers This chapter provides general guidelines for creating 1000BASE-X designs that use RocketIO transceivers for V irtex-II Pr o, V irtex-4, and V irtex-5 devices. Information about RocketIO transceiver and core logic in ...

  • Xilinx 1000BASE-X - page 80

    80 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 7: 1000B ASE-X with RocketIO T ransceiver s R Figure 7-1: 1000B ASE-X Connection to a Virtex-II Pro MGT Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE Virtex-II Pro RocketIO (GT_ETHERNET_1) BREFCLK2 TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2 userclk userclk2 DCM CL ...

  • Xilinx 1000BASE-X - page 81

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 81 UG155 March 24, 2008 Rocke tIO T ransceive r Logic R Vir tex-4 FX De vices The core is design ed to integrate with the V irtex-4 RocketIO MGT . Figur e 7-2 illust rates the connections and logic r equired between the core and MGT—the signal names and logic in the figure pr ecisely mat ...

  • Xilinx 1000BASE-X - page 82

    82 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 7: 1000B ASE-X with RocketIO T ransceiver s R Figure 7- 2: 1000BASE-X Co nnection to Virtex-4 MGT Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE Virtex-4 GT11 RocketIO (used) TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2 userclk userclk2 userclk2 (125MHz) IPAD IPAD br ...

  • Xilinx 1000BASE-X - page 83

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 83 UG155 March 24, 2008 Rocke tIO T ransceive r Logic R Vir tex-5 LXT and SXT De vices The core is designed to integrate with the V irtex-5 RocketIO GTP transceiver . Figur e 7-3 illustrates the connections and lo gic requir ed between the core and the GTP transceiver— the signal names a ...

  • Xilinx 1000BASE-X - page 84

    84 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 7: 1000B ASE-X with RocketIO T ransceiver s R Figure 7-3: 1000B ASE-X Connection to Vir te x-5 GTP T ransceivers Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE Virtex-5 GTP RocketIO (0) TXU S RCLK0 TXU S RCLK20 RXU S RCLK0 RXU S RCLK20 userclk userclk2 rxbufst ...

  • Xilinx 1000BASE-X - page 85

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 85 UG155 March 24, 2008 Rocke tIO T ransceive r Logic R Vir tex-5 FXT De vices The core is designed to integrate with the V irtex-5 RocketIO GTX transceiver . Figure 7-4 illustrates the connections and lo gic requir ed between the core and the GTX trans ceiver— the signal names and logic ...

  • Xilinx 1000BASE-X - page 86

    86 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 7: 1000B ASE-X with RocketIO T ransceiver s R Figure 7-4: 1000B ASE-X Connection to Vir te x-5 GTX T ransceivers Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE Virtex-5 GTP RocketIO (0) TXU S RCLK0 TXU S RCLK20 RXU S RCLK0 RXU S RCLK20 userclk userclk2 rxbufst ...

  • Xilinx 1000BASE-X - page 87

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 87 UG155 March 24, 2008 Clock Sharing Acr oss Multiple Cores wi th Roc ketIO R Cloc k Sharing Acr oss Multiple Cores with Roc ketIO Vir tex-II Pro De vices Figur e 7-5 illustrates sharing clock resources across two instantiations of the cor e on the s a m e h a l f o f t h e d e v i c e w ...

  • Xilinx 1000BASE-X - page 88

    88 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 7: 1000B ASE-X with RocketIO T ransceiver s R Vir tex-4 FX De vices Figur e 7-6 illustrates sharing clock resources across multiple instantiations of the core when using MGT s. Note that the example desi gn, when using the V irtex-4 f amily , ca n be generate ...

  • Xilinx 1000BASE-X - page 89

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 89 UG155 March 24, 2008 Clock Sharing Acr oss Multiple Cores wi th Roc ketIO R Figure 7-6: Clock Management - Multipl e Core Instances, MGTs f or 1000B ASE-X Ethernet 1000BASE-X PCS/PMA or SGMII core userclk userclk2 IP AD b refclkp (250MHz) IP AD b refclkn (250MHz) Virtex-4 GT11CLK_MGT MG ...

  • Xilinx 1000BASE-X - page 90

    90 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 7: 1000B ASE-X with RocketIO T ransceiver s R Vir tex-5 LXT and SXT De vices Figur e 7-7 illustrates sharing clock resources across multiple instantiations of the core when using V ir tex-5 RocketIO GTP transceivers. The example design can be generated to con ...

  • Xilinx 1000BASE-X - page 91

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 91 UG155 March 24, 2008 Clock Sharing Acr oss Multiple Cores wi th Roc ketIO R Figure 7-7: Clock Management - Multiple Core Insta nces, Vir tex-5 Roc ketIO GTP T ransceivers f or 1000BASE-X Ethernet 1000BASE-X PCS/PMA or SGMII core userclk userclk2 Virtex-5 GTP RocketIO (0) CLKIN rocketio_ ...

  • Xilinx 1000BASE-X - page 92

    92 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 7: 1000B ASE-X with RocketIO T ransceiver s R Vir tex-5 FXT De vices Figur e 7-8 illustrates sharing clock resources across multiple instantiations of the core when using V ir tex-5 RocketIO GT X transceivers. The example design can be generated to connect ei ...

  • Xilinx 1000BASE-X - page 93

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 93 UG155 March 24, 2008 Clock Sharing Acr oss Multiple Cores wi th Roc ketIO R Figure 7-8: Clock Management - Multiple Core Insta nces, Vir tex-5 Roc ketIO GTX T ransceivers f or 1000BASE-X Ethernet 1000BASE-X PCS/PMA or SGMII core userclk userclk2 Virtex-5 GTP RocketIO (0) CLKIN rocketio_ ...

  • Xilinx 1000BASE-X - page 94

    94 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 7: 1000B ASE-X with RocketIO T ransceiver s R ...

  • Xilinx 1000BASE-X - page 95

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 95 UG155 March 24, 2008 R Chapter 8 SGMII / Dynamic Standards Switching with RocketIO T ransceivers This chapter provides general guid elines for creating SGMII designs, and desi gns capable of switching between 1000BASE-X and SGMII standards (Dynamic Standards Switching), using a Rocket I ...

  • Xilinx 1000BASE-X - page 96

    96 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 8: SGMII / Dynamic St andar ds Switchin g with Roc ketIO T ransceivers R (see the next section). However , ther e are logical implementations where this can be reliable and has the benefit of lower logic utilization. The Requirement f or the FPGA F abric Rx E ...

  • Xilinx 1000BASE-X - page 97

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 97 UG155 March 24, 2008 Receiver Elastic Buf fer Implementat ions R Considering the 10 Mbps case, we would need 152200/5000 = 31 FIFO entries in the Elastic Buffer above and below the half way point to guarantee that the buf fer will not under or overflow during frame re ception. This assu ...

  • Xilinx 1000BASE-X - page 98

    98 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 8: SGMII / Dynamic St andar ds Switchin g with Roc ketIO T ransceivers R Closely Related Clock Sources Case 1 Figur e 8-2 illustrates a simplified diagram of a common situation wher e the core, in SGMII mode, is interfa ced to an external PHY device . A commo ...

  • Xilinx 1000BASE-X - page 99

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 99 UG155 March 24, 2008 RocketIO Logic with the Fabric Rx Elastic Buffer R Roc ketIO Logic with the F abric Rx Elastic Buffer The example design deliver ed with the core is split between two hierarchical layers, as illustra ted in Figure 4-3 . The block level is designed s o to be instanti ...

  • Xilinx 1000BASE-X - page 100

    100 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 8: SGMII / Dynamic St andar ds Switchin g with Roc ketIO T ransceivers R Figure 8-3: SGMII Connection to a Virtex-II Pr o RocketIO T ransceiver Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE Vir te x-II Pro Rock etIO (GT_CU S T OM) BREFCLK2 TXUSRCLK TXUSRCLK2 ...

  • Xilinx 1000BASE-X - page 101

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 101 UG155 March 24, 2008 RocketIO Logic with the Fabric Rx Elastic Buffer R Vir tex-4 De vices f or SGMII or Dynamic Standards Switching The core is designed to integrate with the V irtex-4 MGT . The connections and logic requir ed between the core and MGT transceiver ar e illustrated in F ...

  • Xilinx 1000BASE-X - page 102

    102 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 8: SGMII / Dynamic St andar ds Switchin g with Roc ketIO T ransceivers R Caution! The PHY connected via SGMII ma y alwa ys provide dynamic SGMII data (when powered up). If not, and if signal_detect is not present, the RX_SIGNAL_DETECT por t of the calibratio ...

  • Xilinx 1000BASE-X - page 103

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 103 UG155 March 24, 2008 RocketIO Logic with the Fabric Rx Elastic Buffer R Vir tex-5 LXT or SXT De vices f or SG MII or Dynamic Standards Switching The core is designed to integrate with th e V irtex-5 RocketIO GTP transceiver . The connections and logic r equired between the cor e and GT ...

  • Xilinx 1000BASE-X - page 104

    104 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 8: SGMII / Dynamic St andar ds Switchin g with Roc ketIO T ransceivers R . Figure 8-5: SGMII Connection to a Virtex-5 Ro cketIO GTP T ransceiver Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE Virtex-5 GTP RocketIO (used) TXU S RCLK0 TXU S RCLK20 RXU S RCLK20 ...

  • Xilinx 1000BASE-X - page 105

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 105 UG155 March 24, 2008 RocketIO Logic with the Fabric Rx Elastic Buffer R Vir tex-5 FXT De vices f or SGMII or Dynamic Standards Switching The core is designed to integrate with th e V irtex-5 RocketIO GTX transceiver . The connections and logic requir ed between the core and GTX transce ...

  • Xilinx 1000BASE-X - page 106

    106 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 8: SGMII / Dynamic St andar ds Switchin g with Roc ketIO T ransceivers R Getting Started Guide and the CORE Generator Guide, at www .xilinx.com/support /softwar e_manuals.htm . Figure 8-6: SGMII Connection to a Virtex-5 Ro cketIO GTX T ransceiver Ethernet 10 ...

  • Xilinx 1000BASE-X - page 107

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 107 UG155 March 24, 2008 Clock Sharing - Multiple Cores with RocketIO , Fabric Elastic Buffer R Cloc k Sharing - Multiple Cores with Roc ketIO , F abric Elastic Buffer Vir tex-II Pro De vices Figur e 8-7 illustrates sharing clock resources across multiple ins tantiations of the core on the ...

  • Xilinx 1000BASE-X - page 108

    108 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 8: SGMII / Dynamic St andar ds Switchin g with Roc ketIO T ransceivers R the device. For mor e information, see the V irtex-II Pro RocketIO T ransceiver User Guide . Each brefclk domain must use its own DCM to de rive its version of userclk and userclk2 . Fi ...

  • Xilinx 1000BASE-X - page 109

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 109 UG155 March 24, 2008 Clock Sharing - Multiple Cores with RocketIO , Fabric Elastic Buffer R Vir tex-4 FX De vices Figur e 8-8 illustrates sharing clock resources across multiple instantiations of the core when using the V irtex-4 RocketIO MGT . Note that the example design, when using ...

  • Xilinx 1000BASE-X - page 110

    110 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 8: SGMII / Dynamic St andar ds Switchin g with Roc ketIO T ransceivers R Figure 8-8: Clock Management with Multiple Core In stances with Virtex -4 MGTs f or SGMII component_n a me _ b lock (Block Lev el) Ethernet 1000BASE-X PCS/PMA or SGMII core userclk user ...

  • Xilinx 1000BASE-X - page 111

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 111 UG155 March 24, 2008 Clock Sharing - Multiple Cores with RocketIO , Fabric Elastic Buffer R Vir tex-5 LXT and SXT De vices Figur e 8-9 illustrates sharing clock resources across multiple instantiations of the core when using the V irtex-5 RocketIO GTP transc eiver . Th e example design ...

  • Xilinx 1000BASE-X - page 112

    112 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 8: SGMII / Dynamic St andar ds Switchin g with Roc ketIO T ransceivers R . Figure 8-9: Clock Management wi th Multiple Core Instances with Vir tex-5 GTP Rocket IO T ransceivers for SGMII component_n a me _ b lock (Block Le vel) Ethernet 1000BASE-X PCS/PMA or ...

  • Xilinx 1000BASE-X - page 113

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 113 UG155 March 24, 2008 Clock Sharing - Multiple Cores with RocketIO , Fabric Elastic Buffer R Vir tex-5 FXT De vices Figur e 8-9 illustrates sharing clock resources across multiple instantiations of the core when using the V irtex-5 RocketIO GTX transc eiver . The example d esign can be ...

  • Xilinx 1000BASE-X - page 114

    114 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 8: SGMII / Dynamic St andar ds Switchin g with Roc ketIO T ransceivers R . Figure 8- 10: Clock Management w ith Multiple Core Instances wi th Virtex-5 GTX Rocket IO T ransceivers for SGMII component_n a me _ b lock (Block Lev el) Ethernet 1000BASE-X PCS/PMA ...

  • Xilinx 1000BASE-X - page 115

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 115 UG155 March 24, 2008 R Chapter 9 Configuration and Status This chapter provides general guidelines fo r configuring and monitoring the Ethernet 1000BASE-X PCS/PMA or SGMII core , including a detailed d escription of the core management regi sters. It also describes Co nfiguration V ect ...

  • Xilinx 1000BASE-X - page 116

    116 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R . The MDIO bus system is a standardized interface for accessing the config uration and status registers of Etherne t PHY devices. In the example illustrated, the Management Host Bu s I /F o f t h e E t he r ne t M AC i s a b le ...

  • Xilinx 1000BASE-X - page 117

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 117 UG155 March 24, 2008 MDIO Management Interface R Write T ransaction Figur e 9-2 shows a write transaction across the MDIO, defined as OP=”01. ” The addressed PHY device (with physical addr ess PHY AD) takes the 16-bit wor d in the Data field and writes it to the register at REGAD. ...

  • Xilinx 1000BASE-X - page 118

    118 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R known by the MDIO master (i n this case an Ethernet MAC), and placed into the PHY AD field of the MDIO frame (see “MDIO T ransactions” ). The PHY AD field for an MDIO fr ame is a 5-bi t binary value capabl e of addr essing ...

  • Xilinx 1000BASE-X - page 119

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 119 UG155 March 24, 2008 Management Regist ers R . Management Register s The contents of the Management Registers can be accessed using the REGAD fie ld of the MDIO frame. Contents will vary depending on the CORE Generator options, and are defined in the following sections in this guide. ? ...

  • Xilinx 1000BASE-X - page 120

    120 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R Register 0: Control Register 2,3 PHY Identifier 4 Auto-Negotiation Advertisement Register 5 Auto-Negotiation Link Part ner Ability Base Register 6 Auto-Negotiation Expansion Register 7 Auto-Negotiation Next Page T ransmit Regis ...

  • Xilinx 1000BASE-X - page 121

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 121 UG155 March 24, 2008 Management Regist ers R 0.13 Speed Selection (LSB) Always returns a 0 for this bit. T ogether with bit 0.6, speed selection of 1000 Mbps is identified Returns 0 0 0.12 Auto- Negotiation Enable 1 = Enable Auto-Negotiation Process 0 = Disable Auto-Negotiation Process ...

  • Xilinx 1000BASE-X - page 122

    122 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R Register 1: Status Register MDIO Register 1: Status Register T able 9- 4: Stat us Register (Regist er 1) Bit(s) Name Description Attributes Default Va l u e 1.15 100BASE-T4 Always returns a ‘0 ’ as 100BASE-T4 is not support ...

  • Xilinx 1000BASE-X - page 123

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 123 UG155 March 24, 2008 Management Regist ers R Registers 2 and 3: PHY Identifiers 1.4 Remote Fault 1 = Remote fault condition detected 0 = No re mote fault condition detecte d Read only Self- clearing on read 0 1.3 Auto- Negotiation Ability Always returns a ‘1’ for this bit to indica ...

  • Xilinx 1000BASE-X - page 124

    124 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R Register 4: A uto-Negotiation Adver tisement T able 9- 5: PHY Identifier (Regist ers 2 and 3) Bit(s) Name Description Att ributes Default V alue 2.15:0 Or ganizationally Unique Identifier Always return 0s re turns 0s 0000000000 ...

  • Xilinx 1000BASE-X - page 125

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 125 UG155 March 24, 2008 Management Regist ers R Register 5: A uto-Negotiation Link P ar tner Base 4.6 Half Duplex Always returns a ‘0’ for this bit since Half Duplex Mode is not supported ret ur n s 0 0 4.5 Full Duplex 1 = Full Duplex Mode is advert ised 0 = Full Duplex Mode is not ad ...

  • Xilinx 1000BASE-X - page 126

    126 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R Register 6: A uto-Negotiation Expansion Register 7: Ne xt P age T ransmit 5.6 Half Duplex 1 = Half Duplex Mode is supported 0 = Half Duplex Mo de is not supported read only 0 5.5 Full Duplex 1 = Full Duplex Mode is supported 0 ...

  • Xilinx 1000BASE-X - page 127

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 127 UG155 March 24, 2008 Management Regist ers R Register 8: Ne xt P age Receive T able 9- 9: Auto-Negotiation Next Page T ransm it (Register 7) Bit(s) Name Description Attr ib utes Default V alue 7.15 Next Page 1 = Additiona l Next Page(s) will follow 0 = Last page read/ write 0 7.14 Rese ...

  • Xilinx 1000BASE-X - page 128

    128 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R Register 15: Extended Status 8.12 Acknowledge 2 1 = Comply with messa ge 0 = Cannot comply with message read only 0 8.1 1 T oggle V alue toggles between subsequent Next Pages read only 0 8.10:0 Message / Unformatte d Code Field ...

  • Xilinx 1000BASE-X - page 129

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 129 UG155 March 24, 2008 Management Regist ers R Register 16: V endor-Specific A uto -Negotiation Interr upt Control 1000BASE-X Standard Without the Optional A uto-Negotiation It is not the intention of this document to f ully describe the 1000BASE-X PCS Regi sters. See clauses 37 and 22 o ...

  • Xilinx 1000BASE-X - page 130

    130 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R Register 0: Control Register MDIO Register 0 : Control Register T able 9- 14: Control Register (Regi ster 0) Bit(s) Name Description Attrib utes Default Va l u e 0.15 Reset 1 = PCS/PMA reset 0 = Normal Operation read/write self ...

  • Xilinx 1000BASE-X - page 131

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 131 UG155 March 24, 2008 Management Regist ers R Register 1: Status Register 0.9 Restart Auto- Negotiation Ignore this bit because Auto-Negotiation is not included. read / w ri te 0 0.8 Duplex Mode Always returns a ‘1’ for this bit to signal Full-Duplex Mode. ret urn s 1 1 0.7 Collisio ...

  • Xilinx 1000BASE-X - page 132

    132 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R 1.10 100BASE-T2 Full Duplex Always returns a ‘0’ for this bit since 100BASE-T2 Full Dupl ex is not supported retu rn s 0 0 1.9 100BASE-T2 Half Duplex Always returns a ‘0’ for this bit since 100BASE-T2 Half Duplex is not ...

  • Xilinx 1000BASE-X - page 133

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 133 UG155 March 24, 2008 Management Regist ers R Registers 2 and 3: Ph y Identifier Register 15: Extended Status MDIO Register s 2 and 3: PHY Identifier T able 9- 16: PHY I dentifier (Re gisters 2 and 3) Bit(s) Name Description A ttributes Default V alue 2.15:0 Or ganizationally Unique Ide ...

  • Xilinx 1000BASE-X - page 134

    134 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R T able 9- 17: Extended Status (Register 15) Bit(s) Name Description Attributes Default Va l u e 15.15 1000BASE-X Full Duplex Always returns a ‘1’ since 1000BASE- X Full Duplex is supported retu rn s 1 1 15.14 1000BASE-X Hal ...

  • Xilinx 1000BASE-X - page 135

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 135 UG155 March 24, 2008 Management Regist ers R SGMII Standard Using the Optional A uto-Negotiation The registers pr ovided for SGMII operation in th is core are adaptations of those defined in IEEE 802.3 clauses 37 and 22. In an SGMII implem entation, two dif ferent types of links exist. ...

  • Xilinx 1000BASE-X - page 136

    136 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R T able 9- 19: SGMII Control (Regis ter 0) Bit(s) Name Description Attributes Default Va l u e 0.15 Reset 1 = Core Reset 0 = Normal Operation rea d /w ri te self clearing 0 0.14 Loopback 1 = Enable Loopback Mode 0 = Disable Loop ...

  • Xilinx 1000BASE-X - page 137

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 137 UG155 March 24, 2008 Management Regist ers R Register 1: SGMII Status 0.5 Unidir ectiona l Enable Enable transmit r egardless of whether a valid link has been established read / w ri te 0 0.4:0 Reserved Always return 0s , writes ignore d returns 0s 00000 T able 9- 19: SGMII Control (Re ...

  • Xilinx 1000BASE-X - page 138

    138 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R 1.7 Unidirectional Ability Always returns ‘1,’ writes i gnored returns 1 1 1.6 MF Preamble Suppression Always returns a ‘1’ for this bit to indicate that Management Frame Preamble Suppression is supported retu rn s 1 1 ...

  • Xilinx 1000BASE-X - page 139

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 139 UG155 March 24, 2008 Management Regist ers R Registers 2 and 3: PHY Identifier Register 4: SGMII A uto-Negotiation Adver tisement MDIO Register s 2 and 3: PHY Identifier T able 9- 21: PHY I dentifier (Re gisters 2 and 3) Bit(s) Name Description Att ributes Default V alue 2.15:0 Or gani ...

  • Xilinx 1000BASE-X - page 140

    140 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R Register 5: SGMII A uto-Negotiation Link P ar tner Ability The Auto-Negotiation Ability Bas e Register (Reg ister 5) contains information r elated to the status of the link between the PHY and its physical link partner across t ...

  • Xilinx 1000BASE-X - page 141

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 141 UG155 March 24, 2008 Management Regist ers R Register 6: SGMII A uto-Negotiation Expansion Register 7: SGMII A uto-Negotiation Next P age T ransmit MDIO Register 6: SGMII A uto-Negotiation Expansion T able 9- 24: SGMII Auto-Nego tiation Expansion (Re gister 6) Bit(s) Name De scription ...

  • Xilinx 1000BASE-X - page 142

    142 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R Register 8: SGMII Ne xt P age Receive 7.12 Acknowled ge 2 1 = Comply with message 0 = Cannot comply with message read/ write 0 7.1 1 T oggle V alue toggles between subsequent Next Pages read only 0 7.10:0 Message / Unformatte d ...

  • Xilinx 1000BASE-X - page 143

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 143 UG155 March 24, 2008 Management Regist ers R Register 15: SGMII Extended Status MDIO Register 15: SGMII Extended Status T able 9- 27: SGM II Extended St atus Regist er (Register 15) Bit(s) Name Description Attrib utes Default V alue 15.15 1000BASE-X Full Duplex Always returns a ‘1’ ...

  • Xilinx 1000BASE-X - page 144

    144 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R Register 16: SGMII A uto-Negotiation Interr upt Control MDIO Register 16: SGMII A uto-Negotiation Interrupt Contr ol T able 9- 28: SGM II A uto-Negot iation Interrupt Cont r ol (Registe r 16) Bit(s) Name Description Attrib utes ...

  • Xilinx 1000BASE-X - page 145

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 145 UG155 March 24, 2008 Management Regist ers R SGMII Standard without the Optional A uto-Negotiation The Registers provid ed for SGMII operation in this cor e are adaptations of those defined in IEEE 802.3 clauses 37 and 22. In an SGMII implem entation, two dif ferent types of links exis ...

  • Xilinx 1000BASE-X - page 146

    146 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R T able 9- 30: SGMII Control (Regis ter 0) Bit(s) Name Description Attributes Default Va l u e 0.15 Reset 1 = Core Reset 0 = Normal Operation rea d /w ri te self clearing 0 0.14 Loopback 1 = Enable Loopback Mode 0 = Disable Loop ...

  • Xilinx 1000BASE-X - page 147

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 147 UG155 March 24, 2008 Management Regist ers R Register 1: SGMII Status 0.5 Unidir ectiona l Enable Enable transmit r egardless of whether a valid link has been established read / w ri te 0 0.4:0 Reserved Always return 0s , writes ignore d returns 0s 00000 T able 9- 30: SGMII Control (Re ...

  • Xilinx 1000BASE-X - page 148

    148 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R 1.7 Unidirectional Ability Always returns ‘1,’ writes i gnored returns 1 1 1.6 MF Preamble Suppression Always returns a ‘1’ for this bit to indicate that Management Frame Preamble Suppression is supported retu rn s 1 1 ...

  • Xilinx 1000BASE-X - page 149

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 149 UG155 March 24, 2008 Management Regist ers R Registers 2 and 3: PHY Identifier Register 4: SGMII A uto-Negotiation Adver tisement MDIO Register s 2 and 3: PHY Identifier T able 9- 32: PHY I dentifier (Re gisters 2 and 3) Bit(s) Name Description Att ributes Default V alue 2.15:0 Or gani ...

  • Xilinx 1000BASE-X - page 150

    150 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R Register 15: SGMII Extended Status Both 1000BASE-X and SGMII Standards Ta b l e 9 - 3 5 describes regi ster 17, the vendor -speci fic Standard Selection Register . This regis ter is only present when the core is ge nerated with ...

  • Xilinx 1000BASE-X - page 151

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 151 UG155 March 24, 2008 Optional Configuration V ector R Register 17: V endor-specific Standard Selection Register Optional Configuration V ector If “MDIO Management Interface” i s omitted, relevant configuration signa ls are br ought out of the cor e. These signals ar e bundled into ...

  • Xilinx 1000BASE-X - page 152

    152 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 9: Configuratio n and Status R These signals may be changed by the user application at any time. The Clock Domain heading denotes the clock domain the configuration signal is registered in befor e use by the core. It is not necessary to driv e the signal fro ...

  • Xilinx 1000BASE-X - page 153

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 153 UG155 March 24, 2008 R Chapter 10 Auto-Negotiation This chapter provides general guidelines for using the Auto-Negotiation funct ion of the Ethernet 1000BASE-X PCS/PMA or SGMII core . Auto-Negotiation is controlled and monitored thr ough the PCS Management Register s and is only availa ...

  • Xilinx 1000BASE-X - page 154

    154 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 10: A uto-Negotiation R a link segment (the link partner) and to de tect corresponding operational modes that the link partner advertises. Figure 10-1 illustrates the operation of 1 000BASE-X Auto- Negotiation. The following describes typical operation when ...

  • Xilinx 1000BASE-X - page 155

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 155 UG155 March 24, 2008 Overvie w of Operation R SGMII Standard Figure 10- 2 illustrates the operation of SGMII Auto-Negotiation. Additional information about SGMII Standard Auto-Negotiation is provided in the f ollowing sections. The SGMII capable PHY has two distin ctive sides to Auto-N ...

  • Xilinx 1000BASE-X - page 156

    156 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 10: A uto-Negotiation R Setting the Configurable Link Timer The optional Auto-Negotiation function has a Link T imer ( link_timer[8:0] ) port. This po rt se ts th e p er io d of th e A ut o- Ne go ti at io n L in k Time r . T hi s p o rt sh ou ld be pe rm an ...

  • Xilinx 1000BASE-X - page 157

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 157 UG155 March 24, 2008 R Chapter 1 1 Dynamic Switching of 1000BASE-X and SGMII Standards This chapter provides general guidelines for using the core to perform dynamic standards switching between 1000BASE-X and SGMII. The co re will only provide this capability if generated with the appr ...

  • Xilinx 1000BASE-X - page 158

    158 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 11: Dynamic Switching of 1000B ASE-X and SGMII Standar ds R Operation of the Core Selecting the P o wer-On / Reset Standard The external port of the cor e, basex_or_sgmii (see “D ynamic Switching Signal Pinou t” in Chapter 2 ), will select the default st ...

  • Xilinx 1000BASE-X - page 159

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 159 UG155 March 24, 2008 Operation of the Core R replace the lin k_timer_value[8:0] port that is use d when the core is genera ted for a single sta ndard. • link_timer_basex[8:0] The value placed on this port is sampled at the beginning of the Auto-Negotiation cycle by the Link T imer wh ...

  • Xilinx 1000BASE-X - page 160

    160 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 11: Dynamic Switching of 1000B ASE-X and SGMII Standar ds R ...

  • Xilinx 1000BASE-X - page 161

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 161 UG155 March 24, 2008 R Chapter 12 Constraining the Cor e This chapter defines the constraint r equirem ents of the Ethernet 1000BASE-X PCS/PM A or SGMII core. An example UCF is provided with the HDL example design for the core to implement the constraints defined in this chapter . See ...

  • Xilinx 1000BASE-X - page 162

    162 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 12: Constrai ning the Core R the HDL sour ce code for the example design and with the information co ntained in Chapter 7, “1000BASE-X with RocketIO T ransceiver s.” Clock P eriod Constraints The clock provided to userclk must be constrained for a clock ...

  • Xilinx 1000BASE-X - page 163

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 163 UG155 March 24, 2008 Required Constraint s R #################################### ######################## # Rocket I/O placement: # #################################### ######################## # Place the Rocket I/O INST "rocketio/mgt" LOC = "GT_X0Y1"; # Locate th ...

  • Xilinx 1000BASE-X - page 164

    164 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 12: Constrai ning the Core R Vir tex-4 Roc ketIO MGTs f o r 1000BASE-X Constraints The constraints defined in this se ction are implemented in the UCF for the example designs deliver ed with the core. Sections fr om the UCF are copied into the following desc ...

  • Xilinx 1000BASE-X - page 165

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 165 UG155 March 24, 2008 Required Constraint s R The following UCF syntax shows these constraints be ing applied. #*********************************** ************************ # PCS/PMA Clock period Constraints: please do not relax * #*********************************** ******************* ...

  • Xilinx 1000BASE-X - page 166

    166 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 12: Constrai ning the Core R Vir tex-4 Roc ketIO MGTs f or SGMII or Dynamic Standards Switching Constraints All the constraints descri bed in the section “V irtex-4 RocketIO MGT s for 1000BASE-X Constraints.” In addition, if the FPGA Fabric Rx El astic B ...

  • Xilinx 1000BASE-X - page 167

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 167 UG155 March 24, 2008 Required Constraint s R Vir tex-5 Roc ketIO GTP T r ansceiv ers f or SGMII or Dynamic Standards Switching Constraints If the core is generated to use the GTP Rx El astic Buf fer , all of the constrai nts apply , as defined in “Clock Period Constraints,” page 16 ...

  • Xilinx 1000BASE-X - page 168

    168 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 12: Constrai ning the Core R NET "*clkin" TNM_NET = "clkin"; TIMESPEC "TS_clkin" = PERIOD "clkin" 8 ns HIGH 50 %; NET "*refclkout" TNM_NET = "refclkou t"; TIMESPEC "TS_refclkout" = PERIOD ...

  • Xilinx 1000BASE-X - page 169

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 169 UG155 March 24, 2008 Required Constraint s R Clock P eriod Constraints The clocks provided to pma_rx_clk0 an d pma_rx_clk1 must be constrained for a clock frequency of 62.5 MHz. The clock pr ovided to gtx_clk must be constrained for a clock freque ncy of 125 MHz. The followi ng UCF syn ...

  • Xilinx 1000BASE-X - page 170

    170 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 12: Constrai ning the Core R In addition, the example design provide s pad locking on the TBI f or several families. This is included as a guideline only , and there are no specific I/O location constraints for this core. TBI Input Setup/Hold Timing Input TB ...

  • Xilinx 1000BASE-X - page 171

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 171 UG155 March 24, 2008 Required Constraint s R INST "core_wrapper/tbi_rx_clk1_dcm" CLKOUT_PHASE_SHIFT = FIXED; INST "core_wrapper/tbi_rx_clk1_dcm" PHASE_SHIFT = -10; INST "core_wrapper/tbi_rx_clk1_dcm" DESKEW_ADJUST = 0; The values of PHASE_SHIFT ar e precon ...

  • Xilinx 1000BASE-X - page 172

    172 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 12: Constrai ning the Core R Vir te x-5 De vices Figure 6-6, page 75 illustrates the TBI input logic pr ov ided by the example design for the V irtex- 5 family . IODELA Y elem ents are inst antiated on the TBI data input path as illustrated: the number of ta ...

  • Xilinx 1000BASE-X - page 173

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 173 UG155 March 24, 2008 Required Constraint s R #################################### ######################## # GMII Clock period Constraints: ple ase do not relax # #################################### ######################## NET "gmii_tx_clk_bufg" TNM_NET = "gm ii_tx_clk ...

  • Xilinx 1000BASE-X - page 174

    174 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 12: Constrai ning the Core R GMII Input Setup/Hold Timing Input GMII timing specification Figure 12- 3 and Ta b l e 1 2 - 2 illustrate the setup and hold time window for the input GMII signals. These are the worst-case data valid window pr esented to the FPG ...

  • Xilinx 1000BASE-X - page 175

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 175 UG155 March 24, 2008 Required Constraint s R timing which is achieved after place-and-route is r eported in the datasheet section of the TRCE report (created by the implement script). For customers fixing their own pinout, the se tup and hold figure s reported in the TRCE report can be ...

  • Xilinx 1000BASE-X - page 176

    176 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 12: Constrai ning the Core R INST "gmii_data_bus[6].delay_gmii_tx d" IDELAY_VALUE = "33"; INST "gmii_data_bus[5].delay_gmii_tx d" IDELAY_VALUE = "33"; INST "gmii_data_bus[4].delay_gmii_tx d" IDELAY_VALUE = &q ...

  • Xilinx 1000BASE-X - page 177

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 177 UG155 March 24, 2008 Required Constraint s R Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Setup/Hold to clock gmii_tx_clk ------------+------------+---------- --+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (ed ...

  • Xilinx 1000BASE-X - page 178

    178 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 12: Constrai ning the Core R ...

  • Xilinx 1000BASE-X - page 179

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 179 UG155 March 24, 2008 R Chapter 13 Interfacing to Other Cor es This chapter describes some additional design con siderations associated wi th implementing the Ethernet 1000BASE-X PCS/ PMA or SGMII cor e with other cores. • 1-Gigabit Ethernet MAC • T ri-Mode Ethernet MAC Integrating ...

  • Xilinx 1000BASE-X - page 180

    180 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 13 : Interfacing to Other Cores R Figure 13-1: 1-Gigabit Ethernet MAC Extended to Include 100 0BASE-X PCS with TBI 1-Gigabit Ethernet MAC LogiCORE gmii_rx_clk gmii_rxd[7:0] gmii_rx_dv gmii_rx_er gmii_txd[7:0] gmii_tx_en gmii_tx_er gtx_clk mdc mdio_in mdio_ou ...

  • Xilinx 1000BASE-X - page 181

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 181 UG155 March 24, 2008 Integrating with the 1- Gigabit Ethernet MAC Core R Integr ation of the 1-Gigabit Ether net MA C Using a Rock etIO T ransceiv er Vir tex-II Pro De vices Figure 13- 2 illustrates the connections and clock manag ement logic requir ed to interface the Ethernet 1000BAS ...

  • Xilinx 1000BASE-X - page 182

    182 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 13 : Interfacing to Other Cores R • If both cores have been generated with th e optional management interface, the M DIO port can be connected up to that of the 1-Gigabit Ethernet MAC cor e, allowing the MAC to access the embedded configuration and status ...

  • Xilinx 1000BASE-X - page 183

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 183 UG155 March 24, 2008 Integrating with the 1- Gigabit Ethernet MAC Core R Features of this configuration include: • Direct internal connections are made between the GMII interfaces between th e two cores. • If both cores have been generated with th e optional management interface, t ...

  • Xilinx 1000BASE-X - page 184

    184 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 13 : Interfacing to Other Cores R Features of this configuration include: • Direct internal connections are made between the GMII interfaces between th e two cores. • If both cores have been generated with th e optional management interface, the M DIO po ...

  • Xilinx 1000BASE-X - page 185

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 185 UG155 March 24, 2008 Integrating with the T ri-Mode Ethernet MA C Core R Features of this configuration include: • Direct internal connections are made between the GMII interfaces between th e two cores. • If both cores have been generated with th e optional management interface, t ...

  • Xilinx 1000BASE-X - page 186

    186 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 13 : Interfacing to Other Cores R • If both cores have been generated with th e optional management interface, the M DIO port can be connected to that of the T ri- Speed Ether net MAC core, allowing the MAC to access the embedded configuration and st atus ...

  • Xilinx 1000BASE-X - page 187

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 187 UG155 March 24, 2008 Integrating with the T ri-Mode Ethernet MA C Core R Figure 13-6 : T ri-Speed Ethernet MAC Extended to use an SGMII with TBI T ri-Speed Ethernet MAC LogiCORE phy emacrxd[7:0] phy emacrxdv phy emacrxer emacphytxd7:0] emacphytx en emacphytx er emacphymclk out phy emac ...

  • Xilinx 1000BASE-X - page 188

    188 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 13 : Interfacing to Other Cores R Integr ation of the T r i-Mode Ether net MA C to Provide SGMII (or Dynamic Switching) Functionality us ing Roc ketIO T ransceiv ers Vir tex-II Pro De vices Figure 13- 7 illustrates the connections and clock manag ement logic ...

  • Xilinx 1000BASE-X - page 189

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 189 UG155 March 24, 2008 Integrating with the T ri-Mode Ethernet MA C Core R Figure 13-7: T ri-S peed Ethernet MAC Extended to use an SGMII in Vi rt ex-II Pro T ri-Speed Ethernet MAC LogiCORE phy emacrxd[7:0] phy emacrxdv phy emacrxer emacphytxd7:0] emacphytx en emacphytx er emacphymclk ou ...

  • Xilinx 1000BASE-X - page 190

    190 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 13 : Interfacing to Other Cores R Vir tex-4 De vices Figure 13- 8 illustrates the connections and clock manag ement logic requir ed to interface the Ethernet 1000BASE-X PCS/PMA or SGMII cor e (when used in SGMII mode with the V irtex-4 MGT) to the T ri-Mode ...

  • Xilinx 1000BASE-X - page 191

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 191 UG155 March 24, 2008 Integrating with the T ri-Mode Ethernet MA C Core R Figure 13-8: T ri-Spee d Ethernet MAC Extended to Use an SGMII in Virtex-4 T r i-Speed Ethernet MAC LogiCORE phy emacrxd[7:0] phy emacrxdv phy emacrxer emacphytxd7:0] emacphytx en emacphytx er emacphymclk out phy ...

  • Xilinx 1000BASE-X - page 192

    192 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 13 : Interfacing to Other Cores R Vir tex -5 LXT and SXT De vices Figure 13- 9 illustrates the connections and clock manag ement logic requir ed to interface the Ethernet 1000BASE-X PCS/PMA or SGMII cor e (when used in SGMII mode with the V irtex-5 GTP) to t ...

  • Xilinx 1000BASE-X - page 193

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 193 UG155 March 24, 2008 Integrating with the T ri-Mode Ethernet MA C Core R Figure 13-9 : T ri-Speed Ethernet MAC Extended to use an SGMII in Virtex-5 LXT/SXT T ri-Speed Ethernet MAC LogiCORE phy emacrxd[7:0] phy emacrxdv phy emacrxer emacphytxd7:0] emacphytx en emacphytx er emacphymclk o ...

  • Xilinx 1000BASE-X - page 194

    194 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 13 : Interfacing to Other Cores R Vir te x-5 FXT De vices Figure 13- 10 illustrates the connections and clock ma nagement logic requir ed to interf ace the Ethernet 1000BASE-X PCS/PMA or SGMII cor e (when used in SGMII mode with the V irtex-5 GTX) to the T r ...

  • Xilinx 1000BASE-X - page 195

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 195 UG155 March 24, 2008 Integrating with the T ri-Mode Ethernet MA C Core R Figure 13-1 0: T ri-Speed Ethernet MA C Extended to use an SGMII i n Virtex-5 FXT T ri-Speed Ethernet MAC LogiCORE phy emacrxd[7:0] phy emacrxdv phy emacrxer emacphytxd7:0] emacphytx en emacphytx er emacphymclk ou ...

  • Xilinx 1000BASE-X - page 196

    196 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 13 : Interfacing to Other Cores R ...

  • Xilinx 1000BASE-X - page 197

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 197 UG155 March 24, 2008 R Chapter 14 Special Design Considerations This chapter describes the unique design cons id erations associated with implementing the Ethernet 1000BASE-X PCS/PMA or SGMII core. P o wer Management No power management considerations ar e recommended for the Ethernet ...

  • Xilinx 1000BASE-X - page 198

    198 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 14: Special Design Considera tions R page 38 ). This instructs the attached PMA SERD ES device to enter loopback mode as illustra ted in Figure 14-1 . Core with Roc k etIO T ransceiv er The loopback path is implemented in the core as illustrated in Figur e 1 ...

  • Xilinx 1000BASE-X - page 199

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 199 UG155 March 24, 2008 Loopbac k R Figure 14-2: Loopbac k Implementation Whe n Using the Core with Roc ketIO T ransceivers Ethernet 1000BASE-X PCS/PMA or SGMII Core RocketIO T ransceiver Tx Rx FPGA Loopback occurs in core PCS Tx Engine PCS Rx Engine Idle Stream loopback control ...

  • Xilinx 1000BASE-X - page 200

    200 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 14: Special Design Considera tions R ...

  • Xilinx 1000BASE-X - page 201

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 201 UG155 March 24, 2008 R Chapter 15 Implementing the Design This chapter describes how to simulate an d implement your d esign containing the Ethernet 1000BASE-X PCS/PMA or SGMII core. Pre-implementation Sim ulation A functional model of the Ethernet 1000B ASE-X PC S/PMA or SGMII core ne ...

  • Xilinx 1000BASE-X - page 202

    202 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 15: Implem enting the De sign R See the XST User Gu ide for more information on cr eating pr oject and synthesis script files, and running the xst pr ogram. XST - V erilog There is a module declaration for the Ethernet 1000BASE-X PCS/PMA or SGMII core in the ...

  • Xilinx 1000BASE-X - page 203

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 203 UG155 March 24, 2008 P ost-Implementation Simulation R layout and timing requir ements specified within t he PCF file. The par command outputs the placed and routed physical design to an NCD file. An example of the par command is: $ par top_level_module_name _map.ncd top_level _module_ ...

  • Xilinx 1000BASE-X - page 204

    204 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Chapter 15: Implem enting the De sign R In addition, use the fol lowing guidlines to determine the simulator type requir ed: Virtex-5 Dev ices V irtex-5 device designs incorporating a Rocket IO transceiver r equire either a V erilog LRM- IEEE 1364-2005 encryption-co ...

  • Xilinx 1000BASE-X - page 205

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 205 UG155 March 24, 2008 R Appendix A Cor e V erification, Compliance, and Inter operability V erification The Ethernet 1000BASE-X PCS/PMA or SGMII cor e has been verified with extensive simulation and har dware verification. Sim ulation A highly parameterizable tr ansaction based test ben ...

  • Xilinx 1000BASE-X - page 206

    206 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix A: Core V erification, Compli ance, and Inter operability R ...

  • Xilinx 1000BASE-X - page 207

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 207 UG155 March 24, 2008 R Appendix B Cor e Latency Core Latency The standalone core does not meet all the latency requirements specified in IEEE 802.3 due to the latency of the Elastic Buff ers in bo th TBI and RocketIO transceiver versions. However , the cor e may be used for backpl ane ...

  • Xilinx 1000BASE-X - page 208

    208 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix B: Core Latency R Latency f or 1000BASE-X PCS and PMA Using a Rock etIO T ransceiv er These measuremen ts are for the core only–they do not include the latency thr ough the Vi r t e x - I I P r o o r Vi r t e x - 4 M G T, Vi r t e x - 5 G T P t r ansceive ...

  • Xilinx 1000BASE-X - page 209

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 209 UG155 March 24, 2008 R Appendix C Calculating the DCM Fixed Phase Shift Va l u e Requirement f or DCM Phase Shifting A DCM is used in the clock path to meet the input setup and hold re quirements when using the core with a TBI (see Chapter 6, “The T en-Bit Interface” ) and with an ...

  • Xilinx 1000BASE-X - page 210

    210 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix C: Calculating the DCM Fixed Phas e Shift V alue R phase shift values must be tested; increments of 4 (52, 56, 60, etc.) correspond to roughly one DCM tap, and consequently provide an appr opriate step s ize. It is not necessary to characterize areas outsid ...

  • Xilinx 1000BASE-X - page 211

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 211 UG155 March 24, 2008 R Appendix D 1000BASE-X State Machines This appendix is intended to serve as a refer ence for the basic operation of the 1000BASE-X IEEE 802.3 clause 36 tr ansmitter and receiv er state machi nes. Intr oduction Ta b l e D - 1 illustrates the Order ed Sets defined i ...

  • Xilinx 1000BASE-X - page 212

    212 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix D: 1000BASE-X State Machines R Star t of Frame Encoding The Ev en T ransmission Case Figure D-1 illustrates the translation of GMII encoding into the code-group stream performed by the PCS T ransmit Engine. This st ream is transmitted out of the core, eithe ...

  • Xilinx 1000BASE-X - page 213

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 213 UG155 March 24, 2008 Start of Frame Encoding R Reception of the Ev en Case Figure D-2 il l us t r at e s t h e re c e pt i on o f th e i n - bo u nd c od e - gro u p st re am , re ce i v ed e it h er se r i a l l y u si n g t h e R oc k e t I O tr a n s c e iv e r , or i n p a r a ll e ...

  • Xilinx 1000BASE-X - page 214

    214 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix D: 1000BASE-X State Machines R Reception of the Odd Case Figure D-4 il l us t r at e s t h e re c e pt i on o f th e i n - bo u nd c od e - gro u p st re am , re ce i v ed e it h er se r i a l l y u si n g t h e R oc k e t I O tr a n s c e iv e r , or i n p ...

  • Xilinx 1000BASE-X - page 215

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 215 UG155 March 24, 2008 End of Frame Encoding R Preamb le Shrinkage As previously described, a s ingle byte of preamble can be lost across the 1000BASE -X system (the actual loss occurs in the 1000BASE-X PCS transmitter state machine). • There is no specific statement for this preamble ...

  • Xilinx 1000BASE-X - page 216

    216 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix D: 1000BASE-X State Machines R Reception of the Ev en Case Figure D-6 il l us t r at e s t h e re c e pt i on o f th e i n - bo u nd c od e - gro u p st re am , re ce i v ed e it h er se r i a l l y u si n g t h e R oc k e t I O tr a n s c e iv e r , or i n ...

  • Xilinx 1000BASE-X - page 217

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 217 UG155 March 24, 2008 End of Frame Encoding R Note: The first Idle to follo w the frame ter mination sequence will be a /I1/ if the frame ended with positive running dispar ity or a /I2/ if the frame ende d with nega tive running dispari ty . This is illustrated as the shaded co de grou ...

  • Xilinx 1000BASE-X - page 218

    218 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix D: 1000BASE-X State Machines R ...

  • Xilinx 1000BASE-X - page 219

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 219 UG155 March 24, 2008 R Appendix E Rx Elastic Buf fer Specifications Th is ap pe nd ix is in te nd ed to s erv e a s a ref e renc e fo r t he Rx El as ti c B uff er si ze s u se d i n t he core, and the relate d maximum frame sizes th at can be used without causing a buffer underflow or ...

  • Xilinx 1000BASE-X - page 220

    220 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix E: Rx Elas tic Buffer Specificatio ns R Vir tex-II Pro and Virtex-5 De vices Consider the V irtex-II Pro and V irtex-5 FPGA example, wher e the shaded ar ea repr esents the usable buffer availability fo r the duration of frame r eception. • If the buffer ...

  • Xilinx 1000BASE-X - page 221

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 221 UG155 March 24, 2008 Rx Elastic Buffer s: Depths and Maximum Frame Sizes R Vir tex-4 FX Consider the V irtex-4 FX case also illustrate d in Figur e E-1 . The thresholds ar e diffe rent to that of the V i rtex-II Pro/V irtex -5 case, but the overall size of the buffer is the same. Inste ...

  • Xilinx 1000BASE-X - page 222

    222 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix E: Rx Elas tic Buffer Specificatio ns R SGMII F abric Rx Elastic Buff er Figure E-2 illustrates the alter native FPGA fabric Rx Elas tic Buf fer depth and thr esholds in Vi r t e x - I I P r o , Vi r t e x - 4 F X a n d Vi r t e x - 5 L X T d e v i c e f a ...

  • Xilinx 1000BASE-X - page 223

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 223 UG155 March 24, 2008 Rx Elastic Buffer s: Depths and Maximum Frame Sizes R TBI Rx Elastic Buff er F or SGMII / Dynamic Switching The Rx Elastic Buffer us ed for the SGMII or Dynamic Standa r ds Switching is identi cal to the method use in “SGMII Fabric Rx Elastic Buf f er .” F or 1 ...

  • Xilinx 1000BASE-X - page 224

    224 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix E: Rx Elas tic Buffer Specificatio ns R Note that this analysi s assumes that the buf fer is appr oximately at the half-full level at the start of the frame reception. As illustrated, ther e are two locations of uncertainty above and below the exact half-fu ...

  • Xilinx 1000BASE-X - page 225

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 225 UG155 March 24, 2008 Clock Co rrection R Idle Character Remo val at 100 Mbps (SGMII) At SGMII, 100 Mb ps, each byte is repeated 10 ti mes. This also applies to the interframe gap period. For this r eason, the minimum of 8 by tes for the 1 Gb ps case corresponds to a minimum of 80 bytes ...

  • Xilinx 1000BASE-X - page 226

    226 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix E: Rx Elas tic Buffer Specificatio ns R Maxim um Frame Sizes for Sustained Frame Reception Sustained frame reception r efers to the maximum size of frames which can be continuously r eceived when each frame is separated by a minimum interframe gap. The size ...

  • Xilinx 1000BASE-X - page 227

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 227 UG155 March 24, 2008 R Appendix F Debugging Guide This appendix provides assistance for debugging the core within a s ystem. For additional help, contact Xilinx by submitting a W ebCase at s upport.xilinx.com/ . General Chec ks • Ensure that all the timing constraints for t he co re ...

  • Xilinx 1000BASE-X - page 228

    228 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix F: Debugging Gu ide R If data is being transmitted and r eceived betw een the core and its link partner , but with a high rate of packet los s, see “Problems with a High Bit Error Rate.” Pr oblems with A uto-Negotiation Determine whether Auto-Negotiatio ...

  • Xilinx 1000BASE-X - page 229

    Ethernet 1000B ASE-X PC S/PMA or SGMII v9.1 www .xilinx.com 229 UG155 March 24, 2008 Prob lems with a High Bit Error Rate R Rock etIO T ransceiv er Specific When using a RocketIO transceiver , perform these additional checks: • Ensur e that the polarities of the TXN/TXP and RXN/RXP lines are not r eversed. If they are, this can be easily fixed by ...

  • Xilinx 1000BASE-X - page 230

    230 www .xilinx.com Ethernet 1000BASE -X PCS/PMA or SGMII v9.1 UG155 March 24, 2008 Appendix F: Debugging Gu ide R Rock etIO T ransceiv er Specific Checks Perform these additional checks when using a RocketIO transceiver: • Directly monitor the following ports of the RocketIO by attaching er ror counters to them, or by triggering on them using Ch ...

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