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Cypress CY7C1373D - page 1
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture CY7C1371D CY7C1373D Cypress Semiconductor Corpora tion • 198 Champion Court • San J ose , CA 95134-1709 • 408-943-2600 Document #: 38-05556 Rev . *F Revised July 09, 2007 Features • No Bus Latency ™ (NoBL ™ ) arch itecture eliminates dead cycles between write and re ...
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Cypress CY7C1373D - page 2
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 2 of 29 Logic Block Diagram – CY7C1371D (512 K x 36) Logic Block Diagram – CY7C1373D (1M x 18) C MODE BW A BW B WE CE1 CE2 CE3 OE READ LOGIC DQs DQP A DQP B DQP C DQP D MEMORY ARRAY E INPUT REGISTER BW C BW D ADDRESS REGISTER WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LOGIC A0&ap ...
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Cypress CY7C1373D - page 3
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 3 of 29 Pin Configurations 100-Pin TQFP Pinout A A A A A1 A0 NC/288M NC/144M V SS V DD NC/36M A A A A A A DQP B DQ B DQ B V DDQ V SS DQ B DQ B DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SS DQ A DQ A DQ A DQ A V SS V DDQ DQ A DQ A DQP A DQP C DQ C DQ C V DDQ V SS DQ C DQ C DQ ...
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Cypress CY7C1373D - page 4
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 4 of 29 100-Pin TQFP Pinout Pin Configurations (continued) A A A A A1 A0 NC/288M NC/144M V SS V DD NC/36M A A A A A A A NC NC V DDQ V SS NC DQP A DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD DQ A DQ A V DDQ V SS DQ A DQ A NC NC V SS V DDQ NC NC NC NC NC NC V DDQ V SS NC NC DQ B DQ B V SS V DDQ D ...
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Cypress CY7C1373D - page 5
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 5 of 29 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R T U V DDQ NC/576M NC/1G DQP C DQ C DQ D DQ C DQ D AA A A V DDQ CE 2 A DQ C V DDQ DQ C V DDQ V DDQ V DDQ DQ D DQ D NC/144M NC V DDQ V DD CLK V DD V SS V SS V SS V SS V SS V SS V SS V SS NC NC NC NC TDO TCK TDI TMS NC ...
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Cypress CY7C1373D - page 6
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 6 of 29 Pin Configurations (continued) 165-Ball FBGA Pinout CY7C137 1D (512K x 36) 234 567 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C CEN A CE2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D DQ D NC/36M NC/72M V DDQ BW D BW A CLK WE V SS V SS V SS ...
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Cypress CY7C1373D - page 7
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 7 of 29 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select o ne of the addr ess locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter . BW A , BW B BW C , BW D Input- Synchronous Byte Write Inpu t s, Activ ...
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Cypress CY7C1373D - page 8
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 8 of 29 Functional Overview The CY7C1371D/CY7 C1373D is a synchronou s flow through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers contro lled by the rising edge of the clock. The clock signal is quali ...
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Cypress CY7C1373D - page 9
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 9 of 29 details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled b y BW X signals. The CY7C1 371D/CY7C1373D provides b yte write capability that is de ...
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Cypress CY7C1373D - page 10
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 10 of 29 T ruth T able [2, 3, 4, 5, 6, 7, 8] Operation Address Used CE 1 CE 2 CE 3 ZZ ADV/LD WE BW X OE CEN CLK DQ Deselect Cycle None H X X L L X X X L L->H T ri-S tate Deselect Cycle None X X H L L X X X L L->H T ri-St ate Deselect Cycle None X L X L L X X X L L->H Tri-S tate Continu ...
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Cypress CY7C1373D - page 11
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 1 1 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1371D/CY7C1373D incorpora tes a serial boundary scan test access port (T AP).This part is fully compliant wi th 1 149.1. T he T AP operates using JEDEC-standard 3.3V or 2.5V IO lo gic levels . The CY7C1371D/CY7C1373 D contains a T AP c ...
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Cypress CY7C1373D - page 12
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 12 of 29 instruction if the controller is placed in a reset state as described in th e previous secti on. When the T AP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for faul t isolatio n of the board le vel serial test ...
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Cypress CY7C1373D - page 13
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 13 of 29 boundary scan path when multiple devices are connected together on a board. EXTEST Output Bus T ri-St ate IEEE S tandard 1 149.1 mandates tha t the T AP controller be able to put th e output bu s into a tri-st ate mode. The boundary scan register h as a special bit locate d at bit #85 ...
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Cypress CY7C1373D - page 14
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 14 of 29 T AP AC Switching Characteristics Over the Operating Range [10, 1 1] Parameter Description Min Max Unit Clock t TCYC TCK Clock Cycle T ime 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH time 20 ns t TL TCK Clock LOW time 20 ns Output Times t TDOV TCK Clock LOW to TDO V alid ...
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Cypress CY7C1373D - page 15
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 15 of 29 3.3V T AP AC T est Conditions Input pulse levels ...... .............. ............ .............. . .V SS to 3.3V Input rise and fall times ......... .............. ........... ........... ...... 1 ns Input timing referenc e levels ............ ........... .............. ...... 1.5V O ...
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Cypress CY7C1373D - page 16
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 16 of 29 Identification Register Definitions Instruction Field CY7C1371D (512K X 36) CY7C1373D (1M X 18) Description Revision Number (31:29) 000 000 Describes the version number Device Depth (28:24) 0101 1 0101 1 Reserved for internal use Device Width (23:18) 001001 001001 Defines memory type a ...
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Cypress CY7C1373D - page 17
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 17 of 29 1 19-Ball BGA Boundary Scan Order [13, 14] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball I D 1 H4 23 F6 45 G4 67 L1 2 T 4 2 4E 7 4 6A 4 6 8 M 2 3T 5 2 5 D 7 4 7 G 3 6 9 N 1 4 T 6 2 6H 7 4 8C 3 7 0P 1 5R 5 2 7 G 6 4 9 B 2 7 1 K 1 6 L 5 2 8E 6 5 0B 3 7 2 L 2 7 R 62 9 D 65 1 A 37 3 ...
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Cypress CY7C1373D - page 18
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 18 of 29 165-Ball BGA Boundary Scan Order [13, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2N 7 3 2 C 1 1 6 2 D 2 3 N10 33 A1 1 63 E2 4P 1 1 3 4 B 1 1 6 4F 2 5P 8 3 5 A 1 0 6 5 G 2 6R 8 3 6 B 1 0 6 6 H 1 7R 9 3 7 A 9 6 7 H 3 8 P 93 8 B 96 8 J 1 9 P10 39 C10 69 K1 10 R10 40 A ...
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Cypress CY7C1373D - page 19
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 19 of 29 Maximum Ratings Exceeding maximum rati ngs may impair the useful life of the device. These user guid elines are not tested. S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emp erature with Power Applied ........... ............................ .. ...
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Cypress CY7C1373D - page 20
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 20 of 29 Cap acit ance [18] Parameter Description T est Conditions 100 TQFP Package 1 19 BGA Package 165 FBGA Package Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 589 p F C CLK Clock Input Capacitance 5 8 9 pF C IO Input/Output Capacitance 5 8 9 pF Thermal Resi ...
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Cypress CY7C1373D - page 21
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 21 of 29 Switching Characteristics Over the Operating Range [23, 24] Parameter Descriptio n 133 MHz 100 MHz Unit Min Max Min Max t POWER [19] 11 m s Clock t CYC Clock Cycle T ime 7.5 10 ns t CH Clock HIGH 2.1 2.5 ns t CL Clock LOW 2.1 2.5 ns Output Times t CDV Data Output V alid After CLK Rise ...
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Cypress CY7C1373D - page 22
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 22 of 29 Switching W aveforms Read/Write W avefo rms [25, 26, 27] WR I T E D(A 1) 123456789 CLK t CY C t CL t CH 10 CE t CE H t CE S WE CE N t C ENH t CE N S BW X AD V/ L D t AH t AS AD D RE S S A1 A2 A3 A4 A5 A6 A7 t DH t DS DQ C O MMAN D t CLZ D(A 1) D(A 2) Q( A 4) Q( A 3) D(A 2+ 1) t DO H t ...
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Cypress CY7C1373D - page 23
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 23 of 29 NOP , ST ALL AND DESELECT Cycles [25, 26, 28] Switching W aveforms (continued) READ Q(A3) 456 789 1 0 A3 A4 A5 D(A4) 123 CLK CE WE CEN BW [A:D] ADV/LD ADDRESS DQ C OMMAND WRITE D(A4) STALL WRITE D(A1) READ Q(A2) STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT DON’T CARE UNDEFINED t C ...
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Cypress CY7C1373D - page 24
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 24 of 29 ZZ Mode T iming [29, 30] Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZR E C AL L I NP UT S ( e x ce p t ZZ) DO N’T CA R E I DDZ Z t ZZI t RZ Z I Ou t p ut s ( Q) Hig h- Z DES ELEC T or REA D O nly Notes: 29. Device must be deselected when ent ering ZZ mode. See truth t a ...
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Cypress CY7C1373D - page 25
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 25 of 29 Ordering Information Not all of the speed, package and temper ature ranges are avail able. Please c ontact your local sales representative or visit www . cypress.com for actual products of fered. Speed (MHz) Ordering Code Package Diagram Part and Package T ype Operating Range 133 CY7C1 ...
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Cypress CY7C1373D - page 26
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 26 of 29 Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMET ...
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Cypress CY7C1373D - page 27
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 27 of 29 Figure 2. 1 19-Ball BGA (14 x 22 x 2.4 mm) (51-851 15) Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF. U T R P N M L K J H G F E D C A B 21 43 65 7 Ø1.00(3X) REF. 7.62 22.00±0.20 14.00±0.20 1.2 ...
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Cypress CY7C1373D - page 28
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 28 of 29 © Cypress Semico nductor Corpor ation, 2004- 2007. The inform ation contai ned herein is sub ject to change wi thout notice. Cypr ess S emiconduct or Corporation a ssumes no responsi bility for the use of any circuitr y other than circui try embodied in a Cy press product. No r does i ...
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Cypress CY7C1373D - page 29
CY7C1371D CY7C1373D Document #: 38-05556 Rev . *F Page 29 of 29 Document History Page Document Title: CY7C1371D/CY7C1373D 18-Mb it (512K x 36/1 Mbit x 18) flow through SRAM with NoBL™ Arc hitecture Document Number: 38-05556 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 2 54513 See ECN RKF New data sheet *A 288531 See ECN SYT E ...
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