Español dropdown-ico

Manual de instrucciones Xilinx 1.8

30 de páginas 0.34 mb
Descargar

Pasar a la página of 30

Summary
  • Xilinx 1.8 - page 1

    R LogiCORE™ IP Endpoint Bloc k Plus v1.8 f or PCI Express® Getting Star ted Guide UG343 J une 27, 2008 ...

  • Xilinx 1.8 - page 2

    www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Xilinx is disclosing this user gui de, manual, rel ease note, and/or sp ecification (the "Documentation") to y ou solely f or use in the de v elopment of designs to operate with Xilinx hardw are de vices. Y ou may not re produce, distribu te, repub lish, downlo ...

  • Xilinx 1.8 - page 3

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com UG343 June 27, 2008 Preface: About This Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx 1.8 - page 4

    www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Dual Core Example De sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Dual Core Directory Structure and Fi le Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 <component name>/example ...

  • Xilinx 1.8 - page 5

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 5 UG343 June 27, 2008 R Pr eface About This Guide The Endpoint Block Plus for P CI Ex pres s® Getting Started Gu ide provides information about generating an Endpoint Block Plus for PCI Expr ess (PCIe ® ) cor e, customizing and simulating the cor e using the pr ovided example design, and ...

  • Xilinx 1.8 - page 6

    6 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Preface: About This Guide R Online Document The following li nking conventions are used in this document: Italic font Refer ences to other manuals See the User Guide for details. Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol, the two nets ...

  • Xilinx 1.8 - page 7

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 7 UG343 June 27, 2008 R Chapter 1 Intr oduction The Endpoint Block Plus for PCI Express is a high-bandwidth , scalable, and r eliable serial interconnect building block for use with V irtex™-5 FPGA devices. This cor e supports V erilog® and VHDL. The example design described in thi s gui ...

  • Xilinx 1.8 - page 8

    8 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 1: Introd uction R performance, pipelined FPGA designs using Xilinx implementation softwar e and User Constraints Files (U CF) is recommended. Additional Core Resour ces For detailed informati on and updates about the cor e, see the fol lowing documents, availa ...

  • Xilinx 1.8 - page 9

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 9 UG343 June 27, 2008 Feedbac k R Document For comments or suggestions about this do cument, please submit a W ebCase from www .xilinx.com/support . Be sure to include the following information: • Document title • Document number • Page number(s) to which your comments r efer • Expl ...

  • Xilinx 1.8 - page 10

    10 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 1: Introd uction R ...

  • Xilinx 1.8 - page 11

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 11 UG343 June 27, 2008 R Chapter 2 Licensing the Cor e This chapter provided licensing options for th e E ndpoint Block Plus for PCI Expr ess cor e, which you must do bef ore using the core in your designs. The cor e is pr ovided under the terms of the Xilinx LogiCORE Site License Agre emen ...

  • Xilinx 1.8 - page 12

    12 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 2: Licensing the Core R Obtaining Y our License Simulatio n Only Eva luation License The Simulation Only Evalua tion license is pr ovided with the CORE Generator system and requir es no license file. Obtaining a Full License T o obtain a Full license, you must ...

  • Xilinx 1.8 - page 13

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 13 UG343 June 27, 2008 R Chapter 3 Quickstart Example Design This chapter provides an overview of the Endpoi nt Block Plus for PCI Ex press example design (both single and dual cor e) and instructio ns for generating the co re. It also includes information about simulati ng and implementing ...

  • Xilinx 1.8 - page 14

    14 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R Figure 3-1: Simula tion Example Design Bloc k Diagram Test Program Endpoint DUT for PCI Express PCI Expr ess Fabric Endpoint Core for PCI Expr ess PIO Design dsport usrapp_tx usrapp_com usrapp_r x Output Logs Downstream Port Mod ...

  • Xilinx 1.8 - page 15

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 15 UG343 June 27, 2008 Overvie w R Implementation Design Ov er vie w The implementation design consists of a simple PIO example that can accept r ead and write transactions and respond to requests, as illustrated in Figure 3-2 . Sour ce code for the example is provided with the core. For mo ...

  • Xilinx 1.8 - page 16

    16 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R Generating the Core T o generate a core using the default values in the CORE Generator Graphical User Interface (GUI), do the following: 1. Start the CORE Generator . For help starting and using the CORE Ge nerator , see the Xil ...

  • Xilinx 1.8 - page 17

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 17 UG343 June 27, 2008 Generating the Core R 4. Set the project options: From the Part tab, select the following options: • Family : V irtex5 • Device : xc5vlx50t • Package : ff1 1 36 • Speed Grade : -1 Note : If an unsupported silicon devi ce is sele cted, the core is dimmed (unava ...

  • Xilinx 1.8 - page 18

    18 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R Sim ulating the Example Design The example design pr ovides a quick way to si mulate and observe the behavior of the cor e. The simulation environment pr ovided with th e Block Plus cor e performs simple memory access tests on t ...

  • Xilinx 1.8 - page 19

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 19 UG343 June 27, 2008 Implementing th e Example Design R 2. Run the script that corresponds to your si mulation tool using one of the following: • VCS : simulate_vcs.sh • Cadence IUS : simulate_ncsim.sh • ModelSim : vsim -do simulate_mti.do Implementing the Example Design After gener ...

  • Xilinx 1.8 - page 20

    20 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R • routed.sdf T iming model Sta ndard Delay File. • mapped.mrp Xilinx map report. • routed.par Xilinx place and route r eport. • routed.twr Xilinx timing analysis report. Th e sc ri pt f ile sta rt s fro m an ED IF/ NG C ...

  • Xilinx 1.8 - page 21

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 21 UG343 June 27, 2008 Directory Structure and File Conten ts R <project director y> The project dir ectory contains all the CORE Generator project files . <project director y>/<component name> The component name directory contains the re lease notes r eadme file pr ovided ...

  • Xilinx 1.8 - page 22

    22 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R <component name>/e xample_design The example design dir ectory contains the ex ample design files pr ovided with the cor e. <component name>/implement The implement directory contains the cor e implementation script ...

  • Xilinx 1.8 - page 23

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 23 UG343 June 27, 2008 Directory Structure and File Conten ts R implement/results The results dir ectory is created by the implem ent script, after which the implement script resul ts are placed in the r esults dir ectory . <component name>/simulation The simulation directory contai n ...

  • Xilinx 1.8 - page 24

    24 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R simulation/dspor t The dsport dire ctory contains the data stre am simulation scripts provided with the core. simulation/functional The functional directory contains functional simulation scripts pr ovided with the core. T able ...

  • Xilinx 1.8 - page 25

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 25 UG343 June 27, 2008 Dual Core Example Design R simulation/tests The tests dir ectory contains test definiti ons for the example te st bench. Dual Core Example Design The dual core example design can be used as a starting point for desi gns with multiple V irtex-5 FPGA PCI Expr ess blocks ...

  • Xilinx 1.8 - page 26

    26 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R Dual Core Director y Structure and File Contents W h e n g e n e r a t i n g t h e B l o c k P l u s c o r e w i t h the V irtex-5 FX70T -FF1 136 (XC5VFX70T -FF1 136) FPGA, the PIO example design source files and s cripts are ge ...

  • Xilinx 1.8 - page 27

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 27 UG343 June 27, 2008 Dual Core Example Design R <component name>/e xample_design The example design dir ectory includes the du al core example design ucf, which varies based on the device selected . e xample_design/dual_core The dual core dir ectory contains the top-leve l and wrapp ...

  • Xilinx 1.8 - page 28

    28 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Chapter 3: Quicks tart Example Design R simulation/functional The functional directory contains the dual cor e example design simulation scripts. <component name>/implement The implement directory contains the dual co re example design implementation script file ...

  • Xilinx 1.8 - page 29

    Endpoint Bloc k Plus v1. 8 for PCI Express www .xilinx.com 29 UG343 June 27, 2008 R Appendix Additional Design Considerations P acka ge Constraints This appendix describes design consi derations specifi c to the Endpoint Block P lus for PCIe core. Ta b l e A - 1 lists the smallest supported devic e an d interface combinations for the Block Plus cor ...

  • Xilinx 1.8 - page 30

    30 www .xilinx.com Endp oint Bloc k Plus v1.8 for PCI Express UG343 June 27, 2008 Appendix Appendix: Additional Design Considera tions R ...

Fabricante Xilinx Categoría Medical Alarms

Los documentos del dispositivo Xilinx 1.8 que obtenemos del fabricante se pueden dividir en varios grupos. Entre ellos están::
- dibujos técnicos Xilinx
- manuales de instrucciones 1.8
- hojas de producto Xilinx
- folletos informativos
- o etiquetas energéticas Xilinx 1.8
Todos son importantes, pero lo más importante desde el punto de vista del usuario de un dispositivo lo encontraremos en el manual de instrucciones Xilinx 1.8.

Un conjunto de documentos determinado como manual de instrucciones se divide también en tipos más detallados, tales como: instrucciones de montaje Xilinx 1.8, instrucciones de servicio, instrucciones cortas o instrucciones de usuario Xilinx 1.8. Dependiendo de la situación debes buscar el documento que necesitas. En nuestra página puedes consultar el manual de instrucciones más popular del producto Xilinx 1.8.

Manuales de instrucciones parecidos

El manual de instrucciones del dispositivo Xilinx 1.8, ¿cómo debería ser?
El manual de instrucciones, también determinado como el manual de usuario o simplemente instrucciones, es un documento técnico que tiene como objetivo ayudar a los usuarios a utilizar Xilinx 1.8. Las instrucciones normalmente las realiza un escritor técnico pero en un lenguaje comprensible para todos los usuarios de Xilinx 1.8.

El manual de instrucciones completo de Xilinx debe contener unos elementos básicos. Una parte de ellos es menos importante, como por ejemplo: la portada / la página principal o las páginas de autor. Sin embargo, lo demás debe facilitarnos la información más importante desde el punto de vista del usuario.

1. Introducción y pistas sobre cómo orientarse con el manual Xilinx 1.8 - Al principio de cada manual se deben encontrar las indicaciones acerca de la manera de usar un manual de instrucciones. Debe contener información sobre dónde encontrar el índice Xilinx 1.8, preguntas frecuentes o problemas más comunes – son los apartados más buscados por los usuarios de cada manual de instrucciones.
2. Índice - listados de todos los consejos acerca de Xilinx 1.8 que encontraremos en el documento
3. Consejos de uso de las funciones básicas del dispositivo Xilinx 1.8 - que deben facilitarnos los primeros pasos durante el uso de Xilinx 1.8
4. Troubleshooting - una secuencia sistematizada de acciones que nos ayudará a diagnosticar los problemas más importantes con Xilinx 1.8
5. FAQ - las preguntas frecuentes
6. Datos de contacto Información acerca de cómo encontrar los datos de contacto del fabricante / servicio de Xilinx 1.8 en cada país si no somos capaces de solucionar el problema por nuestra cuenta.

¿Tienes una pregunta acerca de Xilinx 1.8?

Utiliza el formulario que se encuentra abajo

Si con la ayuda del manual de instrucciones encontrado no has podido solucionar tu problema con Xilinx 1.8, haz una pregunta utilizando el formulario que se encuentra abajo. Si alguno de los usuarios ha tenido un problema parecido con Xilinx 1.8 probablemente compartirá una forma de solucionarlo.

Copia el texto de la imagen

Captcha
Nueva imagen

Comentarios (0)