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Cypress CY7C1294DV18 - page 1
9-Mbit QDR- II™ SRAM 2-W ord Burst Architecture CY7C1292DV18 CY7C1294DV18 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 001-00350 Rev . *A Revised July 20, 2006 Features • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock ...
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Cypress CY7C1294DV18 - page 2
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 2 of 23 Logic Block Diagram (CY7C1292DV18) CLK A (17:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Q [17:0] Control Logic Address Register Reg. Reg. Reg. 18 18 18 36 18 BWS [1:0] V REF Write Add. Decode 18 A (17:0) 18 C C 18 256K x 18 Array 2 ...
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Cypress CY7C1294DV18 - page 3
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 3 of 23 Pin Configurations CY7C1292DV18 (5 12K x 18) 23 4 5 6 7 1 A B C D E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/144M NC/36M BWS 1 K WPS NC/288M Q9 D9 NC NC NC TDO NC NC D13 NC NC NC TCK NC D10 A NC K BWS 0 V SS AAA Q10 V SS V SS V SS V SS V DD A V SS V SS V SS V DD Q1 1 D12 V ...
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Cypress CY7C1294DV18 - page 4
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 4 of 23 Pin Definitions Pin Name I/O Pin Descrip tion D [x:0] Input- Synchronous Data input signals, sampled on the rising edge of K and K clocks d uring va lid write operations . CY7C1292DV18 - D [1 7:0] CY7C1294DV18 - D [3 5:0] WPS Input- Synchronous Write Port Select, active LOW . Sam ...
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Cypress CY7C1294DV18 - page 5
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 5 of 23 Functional Overview The CY7C1292DV18 a nd CY7C1294DV1 8 are synchronou s pipelined Burst SRAMs equipp ed with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the ...
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Cypress CY7C1294DV18 - page 6
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 6 of 23 Byte Write Operations Byte Write operations are supported by the CY7C1292DV18. A Write operation is initiated as described in the Write Opera- tions section above. The bytes that are w ritten are determined by BWS 0 and BWS 1 , which are sampled with each 18-bit da ta word. Asser ...
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Cypress CY7C1294DV18 - page 7
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 7 of 23 Application Example [1] T ruth T able [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ Write Cycle: Load address on the rising e dge of K clock; i nput write data on K and K rising edges. L-H X L D(A + 0) at K(t) ↑ D(A + 1) at K (t) ↑ Read Cycle: Load address on the rising ed ge ...
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Cypress CY7C1294DV18 - page 8
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 8 of 23 Write Cycl e Descriptions (CY7C1294DV18 ) [2, 8] BWS 0 BWS 1 BWS 2 BWS 3 KK Comments L L L L L-H - During the Data portion of a Write sequence, all four bytes (D [35:0] ) are written into the device. L L L L - L-H During the Data portion of a Write sequence, all four bytes (D [35 ...
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Cypress CY7C1294DV18 - page 9
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 9 of 23 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial bo undary scan test access port (T AP) in the FBGA package. This part is fully compliant with IEEE S tandard #1 149.1-1900. The T AP operates u sing JEDEC standard 1.8V I/O logi c levels. Disabling the JT ...
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Cypress CY7C1294DV18 - page 10
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 10 of 23 IDCODE The IDCODE instruction causes a ven dor-specific, 32-bit code to be loaded into the instruction re gister . It also plac es the instruction register be tween the TDI and T DO pins and allow s the IDCODE to be shifted out of the device when th e T AP controller enters the ...
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Cypress CY7C1294DV18 - page 11
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 1 1 of 23 Note: 9. The 0/1 next to each state re present s the value at TMS at the rising edge of TCK. T AP Controller St ate Diagram [9] TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR SELECT IR-SCAN CAPTURE-IR SHIFT -IR EXI ...
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Cypress CY7C1294DV18 - page 12
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 12 of 23 T AP Controller Block Diagram 0 0 1 2 . . 29 30 31 Boundary Scan Register Identification Register 0 1 2 . . . . 106 0 1 2 Instruction Register Bypass Register Selection Circuitry Selection Circuitry T AP Controller TDI TDO TCK TMS T AP Electrical Characteristics Over the Operati ...
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Cypress CY7C1294DV18 - page 13
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 13 of 23 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min. Max. Unit t TCYC TCK Clock Cycle T ime 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Set-up Times t TMSS TMS Set-up to TCK Clock Rise 5 ns t ...
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Cypress CY7C1294DV18 - page 14
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 14 of 23 Identification Register Definitions Instruction Field Va l u e Description CY7C1292DV18 CY7C1294DV18 Revision Number (31:29) 000 000 V ersion number . C y p r e s s D e v i c e I D ( 2 8 : 1 2 ) 1 101001 10100101 10 1 101001 10101001 10 D e f i n e s t h e t y p e o f S R A M . ...
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Cypress CY7C1294DV18 - page 15
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 15 of 23 Boundary Scan Order Bit # Bum p ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 1 1H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 26 N 2 9 9 G 5 6 6 A 8 3 1 J 3 7P 30 1 1F 57 5B 84 2J 4 7N 31 1 1G 58 5A 85 3K 57 R 3 2 9 F 5 9 4 A 8 6 3 J 6 8R 33 10F 60 5C 87 2K 7 8P 34 1 1E 61 4B 88 ...
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Cypress CY7C1294DV18 - page 16
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 16 of 23 Power-Up Sequence in QDR-II SRAM [16] QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined opera tions. Power-Up Sequence • Apply power with DOFF tied HIGH (All other inputs can be HIGH or LOW) —A p p l y V DD before V DDQ —A p p l y ...
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Cypress CY7C1294DV18 - page 17
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 17 of 23 Maximum Ratings (Above which the useful life may be impaired.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... ............................ ...... –55°C to +125°C Supply V oltage on V DD Relati ...
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Cypress CY7C1294DV18 - page 18
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 18 of 23 Note: 22. Unless otherwise noted, test conditions assume sign al transiti on time of 2V/ns, timing reference levels of 0.75V , Vr ef = 0.75V , RQ = 250 Ω , V DDQ = 1.5V , input pulse levels of 0.25V to 1.25V , and output loading of the specified I OL /I OH and load capacit anc ...
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Cypress CY7C1294DV18 - page 19
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 19 of 23 Switching Characteristics Over the Operating Range [22, 23] Cypress Parameter Consortium Parameter Descriptio n 250 MHz 200 MHz 16 7 MHz Unit Min. Max. Min. Max. Min. Max. t POWER t KHKH V DD (T ypical) to the first Access [24] 11 1 m s t CYC t KHKL K Clock and C Clock Cycl e T ...
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Cypress CY7C1294DV18 - page 20
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 20 of 23 Switching W aveforms [27, 28, 29] Read/Write/Deselect Sequence Notes: 27. Q00 refers to outp ut from address A0. Q01 refers to output from t he next internal burst addr ess following A0, i.e., A0 + 1. 28. Output are disabled (High-Z) on e clock cycle after a NOP . 29. In this ex ...
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Cypress CY7C1294DV18 - page 21
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 21 of 23 Ordering Information Not all of the spee d, package and temperature ranges are a vailable. Please c ontact your local sales representative or visit www .cyp ress.com for actual pr oducts offered. Spee d (MHz) Ordering Code Packag e Diagram Package T ype Operating Range 167 CY7C1 ...
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Cypress CY7C1294DV18 - page 22
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 22 of 23 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wit hou t n otice. Cypress Semic onduct or Corporation assumes no responsib ility for the u se of any circuitry o ther than circuitr y embodied in a C ypress produc ...
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Cypress CY7C1294DV18 - page 23
CY7C1292DV18 CY7C1294DV18 Document #: 001-00350 Rev . *A Page 23 of 23 Document History Page Document Title: CY7C1292DV18/CY7C1294DV18 9-Mbit QDR- II™ SRAM 2-Word Burst Architecture Document Number: 001-00350 REV . ECN No. Issue Date Orig. of Change Description o f Change ** 380 737 See ECN SYT Ne w data sheet *A 485631 See ECN NXR Converted fro ...
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