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Cypress CY7C1365C - page 1
9-Mbit (256K x 32) Flow-Through Sync SRAM CY7C1365C Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05690 Rev . *E Revised September 14, 2006 Features • 256K x 32 common I/O • 3.3V core power supply (V DD ) • 2.5V/3.3V I/O power suppl y (V DDQ ) • Fast clock-to-output ...
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Cypress CY7C1365C - page 2
CY7C1365C Document #: 38-05690 Rev . *E Page 2 of 18 ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE A [1:0] ZZ DQ s A 0, A1, A ADV CLK ADSP ADSC BW D BW C BW B BW A BWE CE1 CE2 CE3 OE GW SLEEP CONTROL DQ A BYTE WRITE REGISTER DQ B BYTE WRITE REGISTER DQ C BYTE WRITE REG ...
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Cypress CY7C1365C - page 3
CY7C1365C Document #: 38-05690 Rev . *E Page 3 of 18 Pin Configurations 100-Pin TQFP Pinout (2 Chip Enable) (AJ version) A A A A A 1 A 0 NC NC V SS V DD NC A A A A A A NC DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A NC NC DQ C DQ C V DDQ V SSQ DQ C DQ C DQ C ...
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Cypress CY7C1365C - page 4
CY7C1365C Document #: 38-05690 Rev . *E Page 4 of 18 100-Pin TQFP Pinout (3 Chip Enable) (A version) Pin Configurations (continued) A A A A A 1 A 0 NC NC V SS V DD A A A A A A A NC DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A NC NC DQ C DQ C V DDQ V SSQ DQ C ...
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Cypress CY7C1365C - page 5
CY7C1365C Document #: 38-05690 Rev . *E Page 5 of 18 Pin Descriptions Name TQFP I/O Des cription A0, A1, A 37,36,32,33, 34,35 ,44,45,46, 47,48,49,50,81,82,9 9,100 92 (for 2 Chip Enable V ersion) 43 (for 3 Chip Enable V ersion) Input- Synchronous Addres s Inpu ts used to select one of the 256K addr ess locations . Sampled at the rising edge of the C ...
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Cypress CY7C1365C - page 6
CY7C1365C Document #: 38-05690 Rev . *E Page 6 of 18 V DD 15,41,65, 91 Power Supply Power supply inputs to the core of the device . V SS 17,40,67,90 Ground Gro un d for the co re of the d evice . V DDQ 4,1 1,20,27,54,61,70,77 , I/O Power Supply Power supp ly fo r the I/O circuitry . V SSQ 5,10,21,26,55,60,71,7 6 I/O Ground Ground for the I /O circu ...
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Cypress CY7C1365C - page 7
CY7C1365C Document #: 38-05690 Rev . *E Page 7 of 18 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge o f the clock. Maximum access delay from the clock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1365C supports secondary cache in systems utilizing either a linear or interleaved burst sequ ...
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Cypress CY7C1365C - page 8
CY7C1365C Document #: 38-05690 Rev . *E Page 8 of 18 ZZ Mode Electrical Characteristics Parameter Description T est Conditions Min. Max. Unit I DDZZ Sleep mode standby current ZZ > V DD – 0.2V 50 mA t ZZS Device operation to ZZ ZZ > V DD – 0.2V 2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V 2t CYC ns t ZZI ZZ Active to Sleep current T hi ...
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Cypress CY7C1365C - page 9
CY7C1365C Document #: 38-05690 Rev . *E Page 9 of 18 T ruth T able fo r Read/W rite [3, 4] Function GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte (A, DQP A ) H L HHH L Write Byte (B, DQP B )H L H H L H Write Bytes (B, A, DQP A , DQP B )H L H H L L Write Byte (C, DQP C ) HLHLH H Write Bytes (C, A, DQP C , DQP A ) HLHLHL Writ ...
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Cypress CY7C1365C - page 10
CY7C1365C Document #: 38-05690 Rev . *E Page 10 of 18 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ................ .............. ... –65 ° C to +150 ° C Ambient T e mperature with Power Applied .................... ... .. .............. ...... –55 ° C to +125 ° C S ...
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Cypress CY7C1365C - page 11
CY7C1365C Document #: 38-05690 Rev . *E Page 1 1 of 18 Cap acit ance [10] Parameter Description T est Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 5p F C CLK Clock Inpu t Capacitance 5 p F C I/O Input/Output Capacitance 5 pF Thermal Resist ance [10] Parameter Description T est Conditions 100 ...
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Cypress CY7C1365C - page 12
CY7C1365C Document #: 38-05690 Rev . *E Page 12 of 18 Switching Characteristics Over the Operating Range [1 1, 12] Parameter Description –133 –100 Unit Min. Max. Min. Max. t POWER V DD (T ypical) to the First Access [13] 11 m s Clock t CYC Clock Cycle T ime 7.5 10 ns t CH Clock HIGH 3.0 4.0 ns t CL Clock LOW 3.0 4.0 ns Output Times t CDV Dat a ...
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Cypress CY7C1365C - page 13
CY7C1365C Document #: 38-05690 Rev . *E Page 13 of 18 Timing Diagrams Read Cycle Timing [17] Note: 17. On this diagram, when CE is LOW, CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, C E 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES Data Out (Q) High-Z t CLZ t DOH t CDV t OE ...
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Cypress CY7C1365C - page 14
CY7C1365C Document #: 38-05690 Rev . *E Page 14 of 18 Write Cycle T iming [18, 19] Notes: 18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW [A:D] LOW. 19. The data bus (Q) remains in High- Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed. Timing Diagrams (continued) t CYC t CL CLK t ADH ...
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Cypress CY7C1365C - page 15
CY7C1365C Document #: 38-05690 Rev . *E Page 15 of 18 Read/Write T iming [17, 19, 20] Note: 20. GW is HIGH. Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A2 t CEH t CES Single WRITE D(A3) A3 A4 BURST READ Back-to-Back READs High-Z Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) t WEH t WES t OEHZ t DH t DS t CDV t OELZ A1 A5 A6 ...
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Cypress CY7C1365C - page 16
CY7C1365C Document #: 38-05690 Rev . *E Page 16 of 18 ZZ Mode T iming [21, 22] Ordering Information Not all of the speed, package and temperature ran ges are available . Please cont act your local sales represen tative or visit www .c ypress.com for actual products offered. Spe e d (MHz) Ordering Code Package Diagram Package T ype Operating Range 1 ...
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Cypress CY7C1365C - page 17
CY7C1365C Document #: 38-05690 Rev . *E Page 17 of 18 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor do ...
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Cypress CY7C1365C - page 18
CY7C1365C Document #: 38-05690 Rev . *E Page 18 of 18 Document History Page Document Title: CY7C1365C 9-Mbit (256K x 32) Flow-Throu gh Sync SRAM Document Number: 38 -05690 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 286269 See ECN PCI New da ta sheet *A 3 20834 See ECN PC I Added 133 MHz in th e Ordering Informa tion table Cha ...
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