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Manuale per l’uso Analog Devices ADSP-2186

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  • Analog Devices ADSP-2186 - page 1

    REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analo ...

  • Analog Devices ADSP-2186 - page 2

    ADSP-2186 –2– REV. 0 biased rounding, result free ALU operations, I/O memory trans- fers and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2186 operates with a 30 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-2186? ...

  • Analog Devices ADSP-2186 - page 3

    ADSP-2186 –3– REV. 0 The shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. The internal result (R) bus connects the computational units so the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data addr ...

  • Analog Devices ADSP-2186 - page 4

    ADSP-2186 –4– REV. 0 concurrently on multiplexed pins. In cases where pin func- tionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics. Common-Mode Pins # Input/ Pin of Out- Name(s) Pins put Function RESET 1 I Processor Reset Input BR 1 I Bus Request Input BG 1 O Bus Grant Output BGH 1 ...

  • Analog Devices ADSP-2186 - page 5

    ADSP-2186 –5– REV. 0 To minimize power consumption during power-down, configure the programmable flag as an output when connected to a three- stated buffer. This ensures that the pin will be held at a constant level and not oscillate should the three-state driver’s level hover around the logic switching point. Interrupts The interrupt control ...

  • Analog Devices ADSP-2186 - page 6

    ADSP-2186 –6– REV. 0 Idle When the ADSP-2186 is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle steals still occur. Slow ...

  • Analog Devices ADSP-2186 - page 7

    ADSP-2186 –7– REV. 0 Clock Signals The ADSP-2186 can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal opera- tion. The only exception is while the processor is in the power- down state. For additional information, ...

  • Analog Devices ADSP-2186 - page 8

    ADSP-2186 –8– REV. 0 There are 8K words of memory accessible internally when the PMOVLAY register is set to 0. When PMOVLAY is set to some- thing other than 0, external accesses occur at addresses 0x2000 through 0x3FFF. The external address is generated as shown in Table II. Table II. PMOVLAY Memory A13 A12:0 0 Internal Not Applicable Not Appli ...

  • Analog Devices ADSP-2186 - page 9

    ADSP-2186 –9– REV. 0 Byte Memory The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K × 8. The byte memory space on the ADSP-2186 supports read and write operations as well as ...

  • Analog Devices ADSP-2186 - page 10

    ADSP-2186 –10– REV. 0 Bootstrap Loading (Booting) The ADSP-2186 has two mechanisms to allow automatic load- ing of the internal program memory after reset. The method for booting is controlled by the Mode A, B and C configuration bits as shown in Table VI. These four states can be compressed into two-state bits by allowing an IDMA boot with Mod ...

  • Analog Devices ADSP-2186 - page 11

    ADSP-2186 –11– REV. 0 configured as an input is synchronized to the ADSP-2186’s clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. In addition to the programmable flags, the ADSP-2186 has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and FL2. FL0-FL2 are dedicated outpu ...

  • Analog Devices ADSP-2186 - page 12

    ADSP-2186 –12– REV. 0 The EZ-ICE ® * connects to your target system via a ribbon cable and a 14-pin female plug. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. Target Board Connector for EZ-ICE ® * Probe The EZ-ICE ® * connector (a standard pin strip header) is shown in Figure 7. You must add t ...

  • Analog Devices ADSP-2186 - page 13

    –13– REV. 0 ADSP-2186 RECOMMENDED OPERA TING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit V DD 4.5 5.5 4.5 5.5 V T AMB 0 +70 –40 +85 ° C ELECTRICAL CHARACTERISTICS K/B Grades Parameter Test Conditions Min Typ Max Unit V IH Hi-Level Input Voltage 1, 2 @ V DD = max 2.0 V V IH Hi-Level CLKIN Voltage @ V DD = max 2.2 V V IL Lo-Level ...

  • Analog Devices ADSP-2186 - page 14

    ADSP-2186 –14– REV. 0 ESD SENSITIVITY The ADSP-2186 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur to devices subjected to high energy electrostatic discharges. The ADSP-2186 features proprietary ESD pr ...

  • Analog Devices ADSP-2186 - page 15

    ADSP-2186 –15– REV. 0 ENVIRONMENTAL CONDITIONS Ambient Temperature Rating: T AMB =T CASE – (PD x θ CA ) T CASE = Case Temperature in ° C PD = Power Dissipation in W θ CA = Thermal Resistance (Case-to-Ambient) θ JA = Thermal Resistance (Junction-to-Ambient) θ JC = Thermal Resistance (Junction-to-Case) Package u JA u JC u CA TQFP 50 ° C/W ...

  • Analog Devices ADSP-2186 - page 16

    ADSP-2186 –16– REV. 0 CAPACITIVE LOADING Figures 9 and 10 show the capacitive loading characteristics of the ADSP-2186. C L – pF RISE TIME (0.4V– 2.4V) – ns 30 300 0 50 100 150 200 250 25 15 10 5 0 20 T = +85 ° C V DD = 4.5V Figure 9. Typical Output Rise Time vs. Load Capacitance, C L (at Maximum Ambient Operating Temperature) C L – pF ...

  • Analog Devices ADSP-2186 - page 17

    ADSP-2186 REV. 0 –17– TIMING PARAMETERS Parameter Min Max Unit Clock Signals and Reset Timing Requirements : t CKI CLKIN Period 60 [50] 150 ns t CKIL CLKIN Width Low 20 ns t CKIH CLKIN Width High 20 ns Switching Characteristics: t CKL CLKOUT Width Low 0.5 t CK – 7 ns t CKH CLKOUT Width High 0.5 t CK – 7 ns t CKOH CLKIN High to CLKOUT High 0 ...

  • Analog Devices ADSP-2186 - page 18

    ADSP-2186 REV. 0 –18– TIMING PARAMETERS Parameter Min Max Unit Interrupts and Flag Timing Requirements : t IFS IRQx , FI, or PFx Setup before CLKOUT Low 1, 2, 3, 4 0.25 t CK + 15 ns t IFH IRQx , FI, or PFx Hold after CLKOUT High 1, 2, 3, 4 0.25 t CK ns Switching Characteristics : t FOH Flag Output Hold after CLKOUT Low 5 0.25 t CK – 7 ns t FO ...

  • Analog Devices ADSP-2186 - page 19

    ADSP-2186 REV. 0 –19– Parameter Min Max Unit Bus Request/Grant Timing Requirements : t BH BR Hold after CLKOUT High 1 0.25 t CK + 2 ns t BS BR Setup before CLKOUT Low 1 0.25 t CK + 17 ns Switching Characteristics : t SD CLKOUT High to xMS , RD , WR Disable 0.25 t CK + 10 ns t SDB xMS , RD , WR Disable to BG Low 0 ns t SE BG High to xMS , RD , W ...

  • Analog Devices ADSP-2186 - page 20

    ADSP-2186 REV. 0 –20– TIMING PARAMETERS Parameter Min Max Unit Memory Read Timing Requirements : t RDD RD Low to Data Valid 0.5 t CK – 9 + w ns t AA A0–A13, xMS to Data Valid 0.75 t CK – 10.5 + w ns t RDH Data Hold from RD High 0 ns Switching Characteristics : t RP RD Pulse Width 0.5 t CK – 5 + w ns t CRD CLKOUT High to RD Low 0.25 t CK ...

  • Analog Devices ADSP-2186 - page 21

    ADSP-2186 REV. 0 –21– Parameter Min Max Unit Memory Write Switching Characteristics : t DW Data Setup before WR High 0.5 t CK – 7+ w ns t DH Data Hold after WR High 0.25 t CK – 2 ns t WP WR Pulse Width 0.5 t CK – 5 + w ns t WDE WR Low to Data Enabled 0 ns t ASW A0-A13, xMS Setup before WR Low 0.25 t CK – 6 ns t DDR Data Disable before W ...

  • Analog Devices ADSP-2186 - page 22

    ADSP-2186 REV. 0 –22– TIMING PARAMETERS Parameter Min Max Unit Serial Ports Timing Requirements : t SCK SCLK Period 50 ns t SCS DR/TFS/RFS Setup before SCLK Low 4 ns t SCH DR/TFS/RFS Hold after SCLK Low 7 ns t SCP SCLK IN Width 20 ns Switching Characteristics : t CC CLKOUT High to SCLK OUT 0.25 t CK 0.25 t CK + 10 ns t SCDE SCLK High to DT Enab ...

  • Analog Devices ADSP-2186 - page 23

    ADSP-2186 REV. 0 –23– Parameter Min Max Unit IDMA Address Latch Timing Requirements : t IALP Duration of Address Latch 1, 3 10 ns t IASU IAD15–0 Address Setup before Address Latch End 3 5n s t IAH IAD15–0 Address Hold after Address Latch End 3 2n s t IKA IACK Low before Start of Address Latch 2, 3 0n s t IALS Start of Write or Read after Ad ...

  • Analog Devices ADSP-2186 - page 24

    ADSP-2186 REV. 0 –24– TIMING PARAMETERS Parameter Min Max Unit IDMA Write, Short Write Cycle Timing Requirements : t IKW IACK Low before Start of Write 1 0n s t IWP Duration of Write 1, 2 15 ns t IDSU IAD15–0 Data Setup before End of Write 2, 3, 4 5n s t IDH IAD15–0 Data Hold after End of Write 2, 3, 4 2n s Switching Characteristics : t IKH ...

  • Analog Devices ADSP-2186 - page 25

    ADSP-2186 REV. 0 –25– Parameter Min Max Unit IDMA Write, Long Write Cycle Timing Requirements : t IKW IACK Low before Start of Write 1 0n s t IKSU IAD15–0 Data Setup before IACK Low 2, 3, 4 0.5 t CK + 10 ns t IKH IAD15–0 Data Hold after IACK Low 2, 3, 4 2n s Switching Characteristics : t IKLW Start of Write to IACK Low 4 1.5 t CK ns t IKHW ...

  • Analog Devices ADSP-2186 - page 26

    ADSP-2186 REV. 0 –26– TIMING PARAMETERS Parameter Min Max Unit IDMA Read, Long Read Cycle Timing Requirements : t IKR IACK Low before Start of Read 1 0n s t IRP Duration of Read 1 15 ns Switching Characteristics : t IKHR IACK High after Start of Read 1 15 ns t IKDS IAD15–0 Data Setup before IACK Low 0.5 t CK – 10 ns t IKDH IAD15–0 Data Ho ...

  • Analog Devices ADSP-2186 - page 27

    ADSP-2186 REV. 0 –27– Parameter Min Max Unit IDMA Read, Short Read Cycle Timing Requirements : t IKR IACK Low before Start of Read 1 0n s t IRP Duration of Read 15 ns Switching Characteristics : t IKHR IACK High after Start of Read 1 15 ns t IKDH IAD15–0 Data Hold after End of Read 2 0n s t IKDD IAD15–0 Data Disabled after End of Read 2 10 ...

  • Analog Devices ADSP-2186 - page 28

    ADSP-2186 REV. 0 –28– 100-Lead TQFP Package Pinout 5 4 3 2 7 6 9 8 1 D19 D18 D17 D16 IRQE +PF4 IRQL0 +PF5 GND IRQL1 +PF6 DT0 TFS0 SCLK0 VDD DT1 TFS1 RFS1 DR1 GND SCLK1 ERESET RESET D15 D14 D13 D12 GND D11 D10 D9 VDD GND D8 D7/ IWR D6/ IRD D5/ IAL D4/ IS GND VDD D3/ IACK D2/IAD15 D1/IAD14 D0/IAD13 BG EBG BR EBR A4/IAD3 A5/IAD4 GND A6/IAD5 A7/IAD ...

  • Analog Devices ADSP-2186 - page 29

    ADSP-2186 REV. 0 –29– TQFP Pin Configurations TQFP Pin TQFP Pin TQFP Pin TQFP Pin Number Name Number Name Number Name Number Name 1 A4/ IAD3 26 IRQE + PF4 51 EBR 76 D16 2 A5/ IAD4 27 IRQL0 + PF5 52 BR 77 D17 3 GND 28 GND 53 EBG 78 D18 4 A6/ IAD5 29 IRQL1 + PF6 54 BG 79 D19 5 A7/ IAD6 30 IRQ2 + PF7 55 D0/ IAD13 80 GND 6 A8/ IAD7 31 DT0 56 D1/ IA ...

  • Analog Devices ADSP-2186 - page 30

    ADSP-2186 REV. 0 –30– OUTLINE DIMENSIONS Dimensions shown in mm and (inches). 100-Lead Metric Thin Plastic Quad Flatpack (TQFP) (ST-100) ORDERING GUIDE Ambient Instruction Temperature Rate Package Package Part Number Range (MHz) Description Option* ADSP-2186KST-115 0 ° C to +70 ° C 28.8 100-Lead TQFP ST-100 ADSP-2186BST-115 –40 ° C to +85 ...

  • Analog Devices ADSP-2186 - page 31

    –31– ...

  • Analog Devices ADSP-2186 - page 32

    C2999–6–3/97 PRINTED IN U.S.A. –32– ...

Fabbricante Analog Devices Categoria Computer Hardware

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