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Cypress CY7C1386DV25 - page 1
18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Cypress Semic onductor Corpora tion • 198 Cham pion Cour t • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-05548 Rev . *E Revised Feburary 15, 2007 Features • Supports bus operation up to 250 MHz • Available speed grades ...
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Cypress CY7C1386DV25 - page 2
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 2 of 30 Logic Block Diagram – CY7C1386DV25 /CY7C1386FV25 [3 ] (512K x 36) Logic Block Diagram – CY7C1387DV25 /CY7C1387FV25 [3 ] (1M x 18) ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSP ADSC MODE BW D BW C BW B BW A BWE GW CE 1 CE 2 CE ...
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Cypress CY7C1386DV25 - page 3
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 3 of 30 Pin Configurations A A A A A 1 A 0 NC/72M NC/36M V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQ C V ...
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Cypress CY7C1386DV25 - page 4
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 4 of 30 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R T U V DDQ NC/288M NC/144M DQP C DQ C DQ D DQ C DQ D AA A A ADSP V DDQ A DQ C V DDQ DQ C V DDQ V DDQ V DDQ DQ D DQ D NC NC V DDQ V DD CLK V DD V SS V SS V SS V SS V SS V SS V SS ...
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Cypress CY7C1386DV25 - page 5
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 5 of 30 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1386DV25 (512K x 36) 234 567 1 A B C D E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE 2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D D ...
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Cypress CY7C1386DV25 - page 6
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 6 of 30 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address inputs used to selec t one of the a ddress locations . Sampled at the rising edge of the CLK if AD SP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 [2] are sampled ac ...
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Cypress CY7C1386DV25 - page 7
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 7 of 30 Functional Overview All synchronous inpu ts pass through input registers controlled by the rising edge of th e clock. All data outputs pass through output registers controlled by th e rising edge of the clock. The CY7C1386DV25/CY7C 1387DV25/CY7C13 ...
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Cypress CY7C1386DV25 - page 8
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 8 of 30 The write signals (GW , BWE , and BW X ) and ADV inputs are ignored during this first cycl e. ADSP triggered write accesses require two cl ock cycles to complete. If GW is asserted LOW on the seco nd clock rise, the data presented to the DQ x input ...
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Cypress CY7C1386DV25 - page 9
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 9 of 30 ZZ Mode Electrical Characteristics Parameter Description T est Conditions Min. Max. Unit I DDZZ Sleep mode standby current ZZ > V DD – 0.2V 80 mA t ZZS Device operation to ZZ ZZ > V DD – 0.2V 2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2 ...
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Cypress CY7C1386DV25 - page 10
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 10 of 30 Partial T r uth T able for Read/W rite [5, 10] Function (CY7C1386DV25/CY7C 1386FV25) GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte A – (DQ A and DQP A ) H L HHH L Write Byte B – (DQ B and DQP B )H L H H L H Write Bytes ...
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Cypress CY7C1386DV25 - page 11
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 1 1 of 30 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1386DV25/CY7C 1387DV25/CY7C13 86FV25/ CY7C1387FV25 incorporates a serial boundary scan test access port (T AP).This part is fully compliant with 1 14 9.1. The T AP operates using JEDEC-standard 3. ...
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Cypress CY7C1386DV25 - page 12
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 12 of 30 Instruction Register Three-bit instructions can be serially loaded into the instructio n register . This register is loade d when it is placed between the TDI and TDO balls as show n in the T AP Controller Block Diagram . Upon power u p, the instr ...
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Cypress CY7C1386DV25 - page 13
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 13 of 30 The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required; that is, w hile data captured is shifted out, the preloa ded data can be shifted in. BYP ASS When the BYP ASS instruction is loaded in the instruction reg ...
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Cypress CY7C1386DV25 - page 14
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 14 of 30 T AP AC T est Conditions Input pulse levels ................... ........... .............. .....V SS to 2.5V Input rise and fall time .............. ............ ........... ................ 1 ns Input timing reference levels .................. . ...
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Cypress CY7C1386DV25 - page 15
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 15 of 30 Identification Register Definitions Instruction Field CY7C1386DV25/ CY7C1386FV2 5 CY7C1387DV25/ CY7C1387FV25 Description Revision Number (31:29) 000 000 Describes the version number . Device Depth (28:24) 0101 1 0101 1 Reserved for internal use De ...
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Cypress CY7C1386DV25 - page 16
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 16 of 30 1 19-Ball BGA Boundary Scan Order [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 G4 67 L1 2 T 42 4 E 74 6 A 46 8 M 2 3T 5 2 5 D 7 4 7 G 3 6 9 N 1 4 T 6 2 6 H 74 8 C 37 0 P 1 5R 5 2 7 G 6 4 9 B 2 7 1 K 1 6 L 5 2 8 E ...
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Cypress CY7C1386DV25 - page 17
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 17 of 30 165-Ball BGA Boundary Scan Order [14, 16] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1N 6 3 1 D 1 0 6 1 G 1 2N 7 3 2 C 1 1 6 2 D 2 3N 1 0 3 3 A 1 1 6 3 E 2 4P 1 1 3 4 B 1 1 6 4 F 2 5P 8 3 5 A 1 0 6 5 G 2 6R 8 3 6 B 1 0 6 6 H 1 7R 9 3 7 A 9 6 7 H 3 ...
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Cypress CY7C1386DV25 - page 18
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 18 of 30 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. For user guideline s, not tested. S torage T emperature .............. .............. ..... –65 ° C to +150 ° C Ambient T emperat ure wit h Power Applied . ...
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Cypress CY7C1386DV25 - page 19
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 19 of 30 Cap acit ance [19] Parameter D escription T est Conditions 100 TQFP Package 11 9 B G A Package 165 FBGA Package Unit C IN Input Capacit a nce T A = 25 ° C, f = 1 MHz, V DD /V DDQ = 2.5V 5 8 9 pF C CLK Clock Input Capacitance 5 8 9 pF C IO Input/O ...
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Cypress CY7C1386DV25 - page 20
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 20 of 30 Switching Characteristics Over the Operating Range [20, 21] Parameter Descriptio n 250 MHz 200 MHz 167 MHz Unit Min. Max. Min. Max. Min. Max. t POWER V DD (T ypical) to the first Access [22] 1 11 ms Clock t CYC Clock Cycle Time 4.0 5.0 6.0 ns t CH ...
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Cypress CY7C1386DV25 - page 21
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 21 of 30 Switching W aveforms Read Cycle Timing [26] t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES GW, BWE,BW Data Out (DQ) High-Z t DOH t CO ADV t OEHZ t CO Single READ BURST READ t OEV t OELZ t CHZ Burst wraps around to ...
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Cypress CY7C1386DV25 - page 22
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 22 of 30 Write Cycle T iming [26, 27] Switching W aveforms (continued ) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW X ADV BURST READ BURST WRITE D(A2) D(A2 + 1) D(A3) D(A3 + 1) D(A2 + 3) A2 A3 Extended BURST WRI ...
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Cypress CY7C1386DV25 - page 23
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 23 of 30 Read/Write Cycle Timing [26, 28, 29] Switching W aveforms (continued ) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A2 t CEH t CES Data Out (Q) High-Z ADV Single WRITE D(A3) A4 A5 A6 D(A5) D(A6) Data In (D) BURST READ Back-to- ...
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Cypress CY7C1386DV25 - page 24
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 24 of 30 ZZ Mode T iming [30, 31] Switching W aveforms (continued ) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes 30. Device must be deselected when entering ZZ sleep mod ...
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Cypress CY7C1386DV25 - page 25
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 25 of 30 Ordering Information Not all of the speed, package, and temperature ranges are av ailable. Pl ease contact your local sales representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Co de Package Diagram Part and ...
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Cypress CY7C1386DV25 - page 26
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 26 of 30 250 CY7C1386DV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (1 4 x 20 x 1.4 mm) Pb-Free Commercial CY7C1387DV25-250AXC CY7C1386FV25-250BGC 5 1-851 15 1 19-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1387FV25-250BGC CY7C1386FV25-250BGXC 5 1-851 15 ...
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Cypress CY7C1386DV25 - page 27
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 27 of 30 Package Diagrams Figure 1. 100-Pin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm ...
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Cypress CY7C1386DV25 - page 28
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 28 of 30 Figure 2. 1 19-Ball BGA (14 x 22 x 2.4 mm) (51-851 15) Package Diagrams (continued) 51-851 15-*B [+] Feedback ...
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Cypress CY7C1386DV25 - page 29
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . * E Page 29 of 30 © Cypress Semicond uctor Corporation , 2006-2007. The i nformation cont ained herein i s subject to change witho ut notice. Cypress Semiconductor Corporat ion assumes no responsibility for the use of an y circuitry oth er than circui try embodie ...
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Cypress CY7C1386DV25 - page 30
CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev . *E Page 30 of 30 Document History Page Document Title: CY7C1386DV25/CY7C1 387D V25/CY7C1386FV25/ CY7C1387F V25 18-M bit (512K x 36/1M x 18) Pipelined DCD Sync SRAM Document Number: 38-05548 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 254550 S ...
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