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Cypress CY7C1474BV33の取扱説明書

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Summary
  • Cypress CY7C1474BV33 - page 1

    72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-15031 Rev . *C Revised February 29, 2008 Features ■ Pin-compatible and functionally equivale nt to ZBT ™ ■ Su ...

  • Cypress CY7C1474BV33 - page 2

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 2 of 30 Logic Block Diagram – CY7C1470BV33 (2M x 36) Logic Block Diagram – CY7C1472BV33 (4M x 18) A0, A1, A C MODE BW a BW b WE CE1 CE2 CE3 OE READ LOGIC DQ s DQ P a DQ P b DQ P c DQ P d D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ...

  • Cypress CY7C1474BV33 - page 3

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 3 of 30 Logic Block Diagram – CY7C1474BV33 (1M x 72) A0, A1, A C MODE CE1 CE2 CE3 OE READ LOGIC DQ s DQ P a DQ P b DQ P c DQ P d DQ P e DQ P f DQ P g DQ P h D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRES ...

  • Cypress CY7C1474BV33 - page 4

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 4 of 30 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa DQa V DDQ V SS DQa DQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A CE 1 CE 2 BW a CE 3 V DD V ...

  • Cypress CY7C1474BV33 - page 5

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 5 of 30 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm ) Pinout CY7C1470BV33 (2M x 36) CY7C1472BV33 (4M x 18) 234 567 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c ...

  • Cypress CY7C1474BV33 - page 6

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 6 of 30 Pin Configurations (continued) CY7C1474BV33 (1M × 72) 209-Ball FBGA (14 x 22 x 1.76 mm) Pi nout A B C D E F G H J K L M N P R T U V W 12 34 5 6 7 89 1 1 10 DQg DQg DQg DQg DQg DQg DQg DQg DQc DQc DQc DQc NC DQPg DQh DQh DQh DQh DQd DQd DQd DQd DQPd DQPc DQc DQc DQc ...

  • Cypress CY7C1474BV33 - page 7

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 7 of 30 T able 1. Pin Definitions Pin Name IO T ype Pin Description A0 A1 A Input- Synchronous Address Inputs Used to Select One of the Address Locations . Sampled at the rising edge of the CLK. BW a BW b BW c BW d BW e BW f BW g BW h Input- Synchronous Byte Write Select In ...

  • Cypress CY7C1474BV33 - page 8

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 8 of 30 Functional Overview The CY7C1470BV33, CY7C1472BV33 , and CY7C1474BV33 are synchronous-pipel ined Burst NoBL SRAMs designed specif- ically to eliminate wait states during read or w rite transitions. All synchronous inputs pass through input registers controlled by th ...

  • Cypress CY7C1474BV33 - page 9

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 9 of 30 access (read, write, or deselect) is latched into the Address Register (provided the ap propriate control signals are asserted). On the next clock rise the data presented to DQ and DQP (DQ a,b,c,d /DQP a,b,c,d for CY7C1470BV33, DQ a,b /DQP a,b for CY7C1472BV33, and ...

  • Cypress CY7C1474BV33 - page 10

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 10 of 30 T a ble 4. T ruth T able The truth table for CY7C1470BV33, CY7C1472BV33, and CY7C1474 BV33 follows. [1, 2, 3, 4, 5, 6, 7] Operation Address Used CE ZZ ADV/LD WE BW x OE CEN CLK DQ Deselect Cycl e None H L L X X X L L-H T ri-St ate Continue Deselect Cycl e None X L ...

  • Cypress CY7C1474BV33 - page 11

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 1 1 of 30 T able 5. Partial Write Cycle Description The partial write cycle description for CY7C1470 BV33, CY7C1472BV33, and CY7 C1474BV33 follows. [1, 2, 3, 8] Function (CY7C1470BV33) WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Write Byte a ? ...

  • Cypress CY7C1474BV33 - page 12

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 12 of 30 IEEE 1 149.1 Serial Boun dary Scan (JT AG) The CY7C1470BV33, CY7C1472BV33 , and CY7C1474BV33 incorporates a serial boundary sca n test access port (T AP). This port operates in accordance with IEEE S tandard 1 149.1-1990 but does not have the set of functions requ ...

  • Cypress CY7C1474BV33 - page 13

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 13 of 30 Instruction Register Three-bit instructions can be serially loa ded into the instruction register . Thi s register is loaded when it is placed b etween the TDI and TDO balls as shown i n the “T AP Controller Block Diagram” on page 12 . During power up, the inst ...

  • Cypress CY7C1474BV33 - page 14

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 14 of 30 possible to capture all o ther signals and simply ig nore the value of the CLK captured in the boundary scan register . After the data is captured, it is possible to shift out the data by putting the T AP into the Shif t-DR state. This places the boundary scan regi ...

  • Cypress CY7C1474BV33 - page 15

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 15 of 30 T AP AC Switchin g Characteristics Over the Operating Range [9, 10] Parameter Description Mi n Max Unit Clock t TCYC TCK Clock Cycle T ime 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH time 20 ns t TL TCK Clock LOW time 20 ns Output T imes t TDOV TCK Cl ...

  • Cypress CY7C1474BV33 - page 16

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 16 of 30 3.3V T AP AC T est Conditions Input pulse levels .................... .............. ........... .... V SS to 3.3V Input rise and fall time s.................................... ................ 1 ns Input timing reference levels........ ................. ......... ...

  • Cypress CY7C1474BV33 - page 17

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 17 of 30 T able 6. Iden tification Reg ister Definitions Instruction Field CY7C1470BV33 (2M x 36) CY7C1472BV33 (4M x 18) CY7C1474BV33 (1M x 72) Description Revision Numb er (31:29) 000 000 000 Describes the version numbe r Device Depth (28:24) [12] 0101 1 0101 1 0101 1 Rese ...

  • Cypress CY7C1474BV33 - page 18

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 18 of 30 T a ble 9. Boun dar y Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1C 1 2 1 R 3 4 1 J 1 1 6 1 B 7 2 D1 22 P2 42 K10 62 B6 3E 1 2 3 R 4 4 3J 1 0 6 3 A 6 4D 2 2 4 P 6 4 4 H 1 1 6 4 B 5 5E 2 2 5 R 6 4 5 G 1 1 6 5 A ...

  • Cypress CY7C1474BV33 - page 19

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 19 of 30 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-B all ID Bit # 2 09-Ball ID Bit # 209-Ball ID 1A 1 2 9 T 1 5 7 U 1 0 8 5 B 1 1 2A 2 3 0 T 2 5 8 T 1 1 8 6 B 1 0 3B 1 3 1 U 1 5 9 T 1 0 8 7 A 1 1 4B 2 3 2 U 2 6 0 R 1 1 8 8 A 1 0 5C 1 3 3 V 1 6 1 R 1 0 8 ...

  • Cypress CY7C1474BV33 - page 20

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 20 of 30 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ................ .............. ... –65°C to +150°C Ambient T emperature w ith Power Applied ..................... ...

  • Cypress CY7C1474BV33 - page 21

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 21 of 30 I SB3 Automatic CE Power Down Current—CMOS Inputs Max. V DD , Device Deselected, V IN ≤ 0.3V or V IN > V DDQ − 0.3V , f = f MAX = 1/t CYC 4.0-ns cycle, 250 MHz 245 mA 5.0-ns cycle, 200 MHz 245 mA 6.0-ns cycle, 167 MHz 245 mA I SB4 Automatic CE Power Down C ...

  • Cypress CY7C1474BV33 - page 22

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 22 of 30 Switching Characteristics Over the Operating Range. Timi ng reference is 1.5V when V DDQ = 3.3V and is 1.25V when V DDQ = 2.5V . T e st conditions shown in (a) of “AC T est Loads and W aveforms” on page 21 unless otherwise noted. Parameter Descriptio n –250 ? ...

  • Cypress CY7C1474BV33 - page 23

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 23 of 30 Switching W aveforms Figure 5 shows read-write timing waveform. [20, 21, 22] Figure 5. Read/W rite Timing WRITE D(A1) 123 456789 CLK t CYC t CL t CH 10 CE t CEH t CES WE CEN t CENH t CENS BW x ADV/LD t AH t AS ADDRESS A1 A2 A3 A4 A5 A6 A7 t DH t DS Data I n-Out (DQ ...

  • Cypress CY7C1474BV33 - page 24

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 24 of 30 Figure 6 shows NOP , ST ALL and DESELECT Cycles waveform. [20, 21, 23] Figure 6. NOP , ST ALL and DESELECT Cycles Figure 7 shows ZZ Mode timing wavefo rm. [24, 25] Figure 7. ZZ Mode Timing Switching W aveforms (continued) READ Q(A3) 456 789 1 0 CLK CE WE CEN BWx AD ...

  • Cypress CY7C1474BV33 - page 25

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 25 of 30 Ordering Information Not all of the speed, package and temper ature ranges are availabl e. Please contact your local sales representative or visit www .cypress.com for actual products offered. Speed (MHz) Ordering Co de Package Diagram Part and Package T y pe Opera ...

  • Cypress CY7C1474BV33 - page 26

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 26 of 30 250 CY7C1470BV33-250AXC 51-850 50 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Commercial CY7C1472BV33-250AXC CY7C1470BV33-250BZC 51-85165 165-ball Fi ne- Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1472BV33-250BZC CY7C1470BV33-250BZXC 5 1-85165 1 65-bal ...

  • Cypress CY7C1474BV33 - page 27

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 27 of 30 Package Diagrams Figure 8. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-850 50 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. ...

  • Cypress CY7C1474BV33 - page 28

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 28 of 30 Figure 9. 165-Ball FBGA (1 5 x 17 x 1.4 m m), 51-85165 Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35 1.40 MAX. SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP V ...

  • Cypress CY7C1474BV33 - page 29

    CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 Document #: 001-15031 Rev . *C Page 29 of 30 Figure 10. 209-Ball F BGA (14 x 22 x 1.7 6 mm), 51-85167 Package Diagrams (continued) 51-85167-* * [+] Feedback ...

  • Cypress CY7C1474BV33 - page 30

    Document #: 001-15031 Rev . *C Re vised February 29, 2008 Page 30 of 30 NoBL and No Bu s Latency are trademar ks of Cypress Semicondu ctor Co rporation. ZBT is a trademark of Integrat ed Device T echn ology , Inc. All products and company names me ntioned in this document may be the tr ademarks of their respe ctive hold er s. CY7C1470BV33 CY7C1472B ...

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Cypress CY7C1474BV33のメーカーから受け取ることができるドキュメントは、いくつかのグループに分けられます。その一部は次の通りです:
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