-
Cypress CY7C1339G - page 1
4-Mbit (128K x 32) Pipelined Sync SRAM CY7C1339G Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05520 Rev . *F Revised July 5, 2006 Features • Registered inp uts and outputs for pipelined op er ation • 128K × 32 common I/O architectur e • 3.3V core power supply (V DD ...
-
Cypress CY7C1339G - page 2
CY7C1339G Document #: 38-05520 Rev . *F Page 2 of 18 Pin Configurations Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum Access T ime 2.6 2.8 3.5 4.0 ns Maximum Operat ing Current 325 265 240 225 mA Maximum CMOS S tandby Cu rrent 40 40 40 40 mA A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/18M NC/9M A A A A A A A NC DQ B DQ B V DDQ V SSQ D ...
-
Cypress CY7C1339G - page 3
CY7C1339G Document #: 38-05520 Rev . *F Page 3 of 18 Pin Configurations (continued) Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address In puts used to select one of the 128K address loca tions . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A1, A0 are ...
-
Cypress CY7C1339G - page 4
CY7C1339G Document #: 38-05520 Rev . *F Page 4 of 18 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO ) is 2.6 ns (250-MHz device). The CY7C1339G ...
-
Cypress CY7C1339G - page 5
CY7C1339G Document #: 38-05520 Rev . *F Page 5 of 18 signal. Consecutive single R ead cycles are supported. Once the SRAM is desel ected at clo ck rise by the chip select and either ADSP or ADSC signals, its output will tri-state immedi- ately . Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions a ...
-
Cypress CY7C1339G - page 6
CY7C1339G Document #: 38-05520 Rev . *F Page 6 of 18 T ruth T able [2, 3, 4, 5, 6, 7] Operation Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power-down None H X X L X L X X X L-H T ri-S tate Deselect Cycle, Power-down None L L X L L X X X X L-H T ri-St ate Deselect Cycle, Power-down None L X H L L X X X X L-H T ri-St at ...
-
Cypress CY7C1339G - page 7
CY7C1339G Document #: 38-05520 Rev . *F Page 7 of 18 Partial T ruth T able for Read/W rite [2, 8] Function GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte A – DQ A H L HHH L Write Byte B – DQ B HLH HLH Write Bytes B, A H L H H L L Write Byte C– DQ C HLHLH H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write ...
-
Cypress CY7C1339G - page 8
CY7C1339G Document #: 38-05520 Rev . *F Page 8 of 18 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T e mperature with Power Applied ........... ............................ ...... –55°C to +125°C Supply V olt ...
-
Cypress CY7C1339G - page 9
CY7C1339G Document #: 38-05520 Rev . *F Page 9 of 18 I SB3 Automatic CE Power-down Current—CMOS Inputs V DD = Max, Device Deselected, or V IN ≤ 0.3V or V IN > V DDQ – 0.3V f = f MAX = 1/t CYC 4-ns cycle, 250 MHz 105 mA 5-ns cycle, 200 MHz 95 mA 6-ns cycle, 166 MHz 85 mA 7.5-ns cycle, 133 MHz 75 mA I SB4 Automatic CE Power-down Current—TT ...
-
Cypress CY7C1339G - page 10
CY7C1339G Document #: 38-05520 Rev . *F Page 10 of 18 Switching Characteristics Over the Operating Range [12, 13, 14, 15, 16, 17] Parameter Description –250 –200 –166 –133 Unit Min. Max. Min. Max. Min. Max. Min. Max. t POWER V DD (T ypical) to the first Access [12] 11 11 m s Clock t CYC Clock Cycle T ime 4.0 5.0 6.0 7.5 ns t CH Clock HIGH 1 ...
-
Cypress CY7C1339G - page 11
CY7C1339G Document #: 38-05520 Rev . *F Page 1 1 of 18 Switching W aveforms Read Cycle Timing [18] Note: 18. On this diagram, when CE is LOW , CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW . When CE is HIG H, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES GW, BWE, BW[A:D] D ...
-
Cypress CY7C1339G - page 12
CY7C1339G Document #: 38-05520 Rev . *F Page 12 of 18 Write Cycle T iming [18, 19] Note: 19. Full width write can be initiat ed by either GW LOW; or by GW HIGH, BWE LOW and BW [A:D] LOW . Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW[A :D] D ata Out (Q) High-Z ADV BURST REA ...
-
Cypress CY7C1339G - page 13
CY7C1339G Document #: 38-05520 Rev . *F Page 13 of 18 Read/Write Cycle Timing [18, 20, 21 ] Notes: 20. The data bus (Q) remain s in high-Z following a WRIT E cycl e, unless a new read access is initiated by ADSP or ADSC . 21. GW is HIGH. Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A2 t CEH t CE ...
-
Cypress CY7C1339G - page 14
CY7C1339G Document #: 38-05520 Rev . *F Page 14 of 18 ZZ Mode T iming [22, 23] Notes: 22. Device must be deselected when ente ring ZZ mode. See Cycle Descr iptions t ab le for all possible signal conditi ons to deselect the device. 23. DQs are in high -Z when exiting ZZ sleep mode. Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL ...
-
Cypress CY7C1339G - page 15
CY7C1339G Document #: 38-05520 Rev . *F Page 15 of 18 Ordering Information Not all of the speed, package and temperature ranges are a vailable. Please contact your local s ales representative or visit www . cypress.com for actual product s offered. Speed (MHz) Ordering Code Package Diagram Package T ype Op erating Range 133 CY7 C1339G-133AXC 51-850 ...
-
Cypress CY7C1339G - page 16
CY7C1339G Document #: 38-05520 Rev . *F Page 16 of 18 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0.30±0 ...
-
Cypress CY7C1339G - page 17
CY7C1339G Document #: 38-05520 Rev . *F Page 17 of 18 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor do ...
-
Cypress CY7C1339G - page 18
CY7C1339G Document #: 38-05520 Rev . *F Page 18 of 18 Document History Page Document Title: CY7C1339G 4-Mbit (128K x 32) Pipeline d Syn c SRAM Document Number: 38-05520 REV . ECN NO. Issue Date Orig. of Change Description of Cha ng e ** 22 436 8 See ECN RKF New data sheet *A 288909 See ECN VBL In Ordering Info section, Cha nged TQFP to PB-free TQFP ...
Cypress CY7C1339Gについてご質問がありますか？
次のフォームを使用してください
見つけた説明書を読んでもCypress CY7C1339Gの問題を解決できない場合、下記のフォームを使用して質問をしましょう。ユーザーのどなたかがCypress CY7C1339Gで同様の問題を抱えていた場合、その解決方法を共有したいと考えるかもしれません。