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Cypress CY7C1305BV25 - page 1
18-Mbit Burst of 4 Pipelined SRAM with Q DR™ Architecture CY7C1307BV25 CY7C1305BV25 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05630 Rev . *A Revised April 3, 2006 Features • Separate independent Read and Write data ports • Supports concurrent transactions • 167- ...
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Cypress CY7C1305BV25 - page 2
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 2 of 21 Selection Guide CY7C1305BV25-167 CY7C1307BV25-167 Unit Maximum Operating Freq uency 167 MHz Maximum Operating Current 400 mA 256Kx18 Array CLK A [17:0] Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Q [17:0] Control Logic Address Register ...
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Cypress CY7C1305BV25 - page 3
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 3 of 21 Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm ) Pinout CY7C1305BV25 (1M x 18 ) 1 2 3 4 5 678 9 1 0 1 1 A NC GND/ 144M NC/ 36M WPS BWS 1 K NC RPS A GND/ 72M NC B NC Q9 D9 A NC K BWS 0 AN C N C Q 8 C NC NC D10 VSS A NC A VSS NC Q7 D8 D NC D1 1 Q10 VSS VSS VSS VSS VSS NC NC D7 ...
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Cypress CY7C1305BV25 - page 4
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 4 of 21 Pin Definitions Name I/O Description D [x:0] Input- Synchronous Data input signals, sampled on the ris ing edge of K and K clocks during valid write operations . CY7C1305BV25 – D [17:0] CY7C1307BV25 – D [35:0] WPS Input- Synchronous Write Port Select, active LOW . Sampled on t ...
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Cypress CY7C1305BV25 - page 5
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 5 of 21 Introduction Functional Overview The CY7C1305BV25/CY7C1307BV25 are synchro nous pipelined Burst SRAMs equipp ed with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write Port is dedicated to Write operations. Data flows into the SRAM throu ...
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Cypress CY7C1305BV25 - page 6
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 6 of 21 When deselected, the wr ite po rt will ign ore all i npu ts after the pending Write operations have been completed . Byte Write Operations Byte Write operations are supported by th e CY7C1305BV25. A write operation is initiate d as described in the Write Operation section above . ...
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Cypress CY7C1305BV25 - page 7
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 7 of 21 T ruth T able [2, 3, 4, 5, 6, 7, 8, 9] Operation K RPS WPS DQ DQ DQ DQ Write Cycle : Load address on the rising edge of K; wait one cycle; input write data on two consecutive K and K rising edges. L-H H [8] L [9] D(A+00) at K(t+1) ↑ D(A+01) at K (t+1) ↑ D(A+10) at K(t+2) ↑ D ...
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Cypress CY7C1305BV25 - page 8
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 8 of 21 Write Cycl e Descriptions (CY7C1307BV25) [2, 10 ] BWS 0 BWS 1 BWS 2 BWS 3 KK Comment s L L L L L-H – During the Data portion of a Write sequence, all four bytes (D [35:0] ) are written into the device. L L L L – L-H During the Data portion of a Write sequence, all four bytes ( ...
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Cypress CY7C1305BV25 - page 9
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 9 of 21 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial bo undary scan test access port (T AP) in the FBGA package. This part is fully compliant with IEEE S tandard #1 149 .1-1900. The T AP operates using JEDEC standard 2.5V I/O logi c levels. Disabling the JT A ...
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Cypress CY7C1305BV25 - page 10
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 10 of 21 is loaded into the instruction register upon power-up or whenever the T AP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction caus es the b oundary scan register to be connected between th e TDI and TDO pins when th e T AP controller is in a Shift-DR ...
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Cypress CY7C1305BV25 - page 11
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 1 1 of 21 T AP Controller St ate Diagram [1 1] Note: 1 1. The 0/1 next to each state re presents the value at TMS at th e rising edge of TCK. TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR SELECT IR-SCAN CAPTURE-IR SHIFT -IR ...
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Cypress CY7C1305BV25 - page 12
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 12 of 21 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating R ange [12, 15, 17] Parameter Description T est Conditions Min. Max. Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.7 V V OH2 Output HIGH V oltage I OH = − 100 µ A2 . 1 V V OL1 Output LOW V o ...
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Cypress CY7C1305BV25 - page 13
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 13 of 21 Output Times t TDOV TCK Clock LOW to TDO V alid 20 ns t TDOX TCK Clock LOW to TDO Invalid 0 ns T AP Timing and T est Conditions [1 4] Identification Register Definitions Instruction Field Va l u e Descr iption CY7C1305BV25 CY7C1307BV25 Revision Number (31:29) 000 000 V ersio n nu ...
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Cypress CY7C1305BV25 - page 14
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 14 of 21 Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Inpu t/Output ring contents. IDCODE 001 Loads the ID registe r with the vendor ID code and place s the register between ...
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Cypress CY7C1305BV25 - page 15
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 15 of 21 Boundary Scan Order Bit # Bum p ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11 H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11 F 57 5B 84 2J 4 7N 31 11 G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11 E 61 4B 88 1K 8 9R 35 1 ...
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Cypress CY7C1305BV25 - page 16
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 16 of 21 Maximum Ratings (Above which the useful life may be impaired.) S torage T e mperature .............. .................. –65°C to + 150°C Ambient T emperature with Power Applied ........... ............................ ..... –55°C to + 125°C Supply V oltage on V DD Relativ ...
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Cypress CY7C1305BV25 - page 17
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 17 of 21 Cap acit ance [22] Parameter Descript ion T es t Conditions Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 2.5V . V DDQ = 1.5V 5p F C CLK Clock Input Capacitance 6 pF C O Output Capacitance 7 pF AC T est Loads and W aveforms 1.25V 0.25V R = 50 Ω 5p F ALL INPUT ...
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Cypress CY7C1305BV25 - page 18
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 18 of 21 Switching Characteristics Over the Operating Range [23] Cypress Parameter Consortium Parameter Description 167 MHz Unit Min. Max. t Power [24] V CC (typical) to the First Access Read or Write 10 µ s Cycle Time t CYC t KHKH K Clock and C Clock Cycle T ime 6.0 ns t KH t KHKL Input ...
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Cypress CY7C1305BV25 - page 19
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 19 of 21 Switching W aveforms [27, 28, 29] Notes: 27. Q00 refers to output from address A0. Q01 refers to output from the ne xt internal burst address follo wing A0, i.e., A0+1. 28. Outputs are disabled (High- Z) one clock cycle after a NOP . 29. In this example, if address A2 = A1 then d ...
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Cypress CY7C1305BV25 - page 20
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 20 of 21 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress ...
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Cypress CY7C1305BV25 - page 21
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev . *A Page 21 of 21 Document History Page Document Title: CY7C1305BV25/CY7C1307BV25 18 -Mb it Burst of Four Pipelined SRAM with QDR™ Architecture Document Number: 38-05630 REV . ECN NO. Issue Date Orig. o f Change Description of Change ** 253049 See ECN SYT Ne w Data Sheet *A 436864 See ECN NXR Co ...
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