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Cypress CY7C1336H - page 1
PRELIMINARY 2-Mbit (64K x 32) Flow-Through Sync SRAM CY7C1336H Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 001-00210 Rev . *A Revised February 6, 2006 Features • 64K x 32 common I/O • 3.3V core power supply • 3.3V I/O supp ly • Fast clock-to-output times — 6.5 ns ( ...
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Cypress CY7C1336H - page 2
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 2 of 15 Selection Guide 133 MHz 100 MHz Unit Maximum Access T i me 6.5 8.0 ns Maximum Operating Current 225 205 mA Maximum S tandby Curre nt 40 40 mA Pin Configuration 100-pin TQFP Pinout A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/9M A A A A A NC/4M NC DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V ...
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Cypress CY7C1336H - page 3
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 3 of 15 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address Inputs us ed to select one of the 64K address locations . Sampl ed at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A [1:0] feed the 2-bit counter . B ...
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Cypress CY7C1336H - page 4
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 4 of 15 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge o f the clock. Maximum access delay from the clock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1336H supports secondary cache in systems utilizing either a linear or interleave ...
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Cypress CY7C1336H - page 5
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 5 of 15 ZZ Mode Electrical Characteristics Parameter Description T est Conditions Min. Max. Unit I DDZZ Sleep mode standby current ZZ > V DD – 0.2V 40 mA t ZZS Device operation to ZZ ZZ > V DD – 0.2V 2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V 2t CYC ns t ZZI ZZ Active to sleep ...
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Cypress CY7C1336H - page 6
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 6 of 15 T ruth T able for Read/Write [2, 3] Function GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte (A, DQP A ) H L HHH L Write Byte (B, DQP B )H L H H L H Write Bytes (B, A, DQP A , DQP B )H L H H L L Write Byte (C, DQP C ) HLHLH H Write Bytes (C, A, DQP C , DQP A ) ...
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Cypress CY7C1336H - page 7
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 7 of 15 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ................ .............. ... –65 ° C to +150 ° C Ambient T e mperature with Power Applied ................. ... ... .............. ........ –55 ° C to ...
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Cypress CY7C1336H - page 8
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 8 of 15 Cap acit ance [9] Parameter Description T est Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V , V DDQ = 3.3V 5p F C CLK Clock Input Capacitance 5 pF C I/O Input/Output Capacitance 5 pF Thermal Resist ance [9] Parameter Description T e st Con ...
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Cypress CY7C1336H - page 9
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 9 of 15 Switching Characteristics Over the Operating Range [10, 1 1] Parameter Descript ion 133 MHz 100 MHz Unit Min. Max. Min. Max. t POWER V DD (T ypical) to the First Access [12] 1 1 ms Clock t CYC Clock Cycle T ime 7.5 10 ns t CH Clock HIGH 2.5 4.0 ns t CL Clock LOW 2.5 4.0 ns Output Tim ...
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Cypress CY7C1336H - page 10
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 10 of 15 Timing Diagrams Read Cycle Timing [16] Note: 16. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES Data Out (Q) High-Z t CLZ t DOH ...
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Cypress CY7C1336H - page 11
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 1 1 of 15 Write Cycle Timing [16, 17] Note: 17. Full width Write can be initiated by either GW LO W; or by GW HIGH, BWE LOW and BW [A:D] LOW. Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D ...
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Cypress CY7C1336H - page 12
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 12 of 15 Read/Write T iming [16, 18, 19] Notes: 18. The data bus (Q) remains in Hi gh-Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed. 19. GW is HIGH. Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A2 t CEH t CES Single WRITE D(A3) A ...
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Cypress CY7C1336H - page 13
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 13 of 15 ZZ Mode Timing [20, 21] Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. DQs are in High-Z when exiting ZZ sleep mode. Timing Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL ...
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Cypress CY7C1336H - page 14
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 14 of 15 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress pro ...
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Cypress CY7C1336H - page 15
PRELIMINARY CY7C1336H Document #: 001-00210 Rev . *A Page 15 of 15 Document History Page Document Title: CY7C1336H 2-Mbit (64K x 32) Flow-Through Sync SRAM Document Number: 00 1-00210 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 347377 See ECN PCI New Data Sheet *A 428408 See ECN NXR Changed address of Cypress Semiconducto r Co ...
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