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Manual Cypress CY7C1464AV25

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  • Cypress CY7C1464AV25 - page 1

    36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05354 Rev . *D Revised June 22, 2006 Features • Pin-comp atible and functionally equiv a le nt to ZBT™ ? ...

  • Cypress CY7C1464AV25 - page 2

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 2 of 27 Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Access T i me 2.6 3.2 3.4 ns Maximum Operating Current 435 385 335 mA Maximum CMOS S tandby Current 120 120 120 mA A0, A1, A C MODE BW a BW b WE CE1 CE2 CE3 OE READ LOGIC DQs DQP a DQP b D A T A S T E E R I N G O ...

  • Cypress CY7C1464AV25 - page 3

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 3 of 27 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa DQa V DDQ V SS DQa DQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A CE 1 CE 2 BW a CE 3 V DD ...

  • Cypress CY7C1464AV25 - page 4

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 4 of 27 Pin Configurations (continued) 23 4 567 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/72M V DDQ BW d BW a CLK WE V SS V SS V SS V SS V DDQ V SS V DD V SS ...

  • Cypress CY7C1464AV25 - page 5

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 5 of 27 Pin Configurations (continued) A B C D E F G H J K L M N P R T U V W 123456789 1 1 10 DQg DQg DQg DQg DQg DQg DQg DQg DQc DQc DQc DQc NC DQPg DQh DQh DQh DQh DQd DQd DQd DQd DQPd DQPc DQc DQc DQc DQc NC DQh DQh DQh DQh DQPh DQd DQd DQd DQd DQb DQb DQb DQb DQb DQb D ...

  • Cypress CY7C1464AV25 - page 6

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 6 of 27 CE 1 Input- Synchronous Chip Enable 1 Inp ut, active LOW . Sampled on the rising edge of CLK. Used in conjunction wi th CE 2 and CE 3 to select/deselect the device. CE 2 Input- Synchronous Chip Enable 2 Input, active HIGH . Sampled on the rising edge of CL K. Used ...

  • Cypress CY7C1464AV25 - page 7

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 7 of 27 Functional Overview The CY7C1460A V25/CY7C1462A V25/CY7C1464A V25 are synchronous-pipel ined Burst NoBL SRAMs designed specifi- cally to eliminate wait states during Write/Read transitions. All synchronous inp uts pass through input registers controlled by the risi ...

  • Cypress CY7C1464AV25 - page 8

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 8 of 27 CY7C1460A V25, BW a,b,c,d for CY7C1460A V25 and BW a,b for CY7C1462A V25) inputs must be driven in each cycle of the burst write in order to writ e the correc t bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a p ...

  • Cypress CY7C1464AV25 - page 9

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 9 of 27 Partial Write Cycle Description [1, 2, 3, 8] Function (CY7C1460A V25) WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Wri te Byte a – (D Q a and DQP a ) L HHH L Wri te Byte b – (D Q b and DQP b )L H H L H Write Bytes b, a L H H L L Wr ...

  • Cypress CY7C1464AV25 - page 10

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 10 of 27 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1460A V25/CY7C1462A V25/CY7C1464A V25 incor- porates a serial boundary scan test access port (T AP). This part is fully compliant with 1 149.1 . The T AP operates using JEDEC-standard 2.5V/1.8V I/O logic level. The ...

  • Cypress CY7C1464AV25 - page 11

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 1 1 of 27 When the T AP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board -level serial test data path. Byp ass Register T o save time when serially shifting data throug ...

  • Cypress CY7C1464AV25 - page 12

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 12 of 27 When this scan cell, called the “extest outpu t bus tri-state,” is latched into the prel oad register during the “Update-DR” state in the T AP controller , it will directly control the state of the output (Q-bus) pins, when t he EXTEST is entered as the cu ...

  • Cypress CY7C1464AV25 - page 13

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 13 of 27 2.5V T AP AC T est Conditions Input pulse levels ........... ........... .............. ........... V SS to 2.5V Input rise and fall time . ......... .. ... ........... ... ........... ... ......... 1 ns Input timing reference levels ............... .............. ...

  • Cypress CY7C1464AV25 - page 14

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 14 of 27 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order (165-ball FBGA package) 89 89 – Boundary Scan Order (209-ball FBGA package) – – 138 Identification Codes Instruction ...

  • Cypress CY7C1464AV25 - page 15

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 15 of 27 165-ball FBGA Boundary Scan Order [12] CY7C1460A V25 (1M x 36), CY7C1462A V25 (2M x 18) Bit# Ball ID Bit# Ball ID Bit# Ball ID Bit# Ball ID 1N 6 2 6 E 1 1 5 1 A 3 7 6 N 1 2N 7 2 7 D 1 1 5 2 A 2 7 7 N 2 3N 1 0 2 8 G 1 0 5 3B 2 7 8P 1 4P 1 1 2 9 F 1 0 5 4 C 2 7 9 R ...

  • Cypress CY7C1464AV25 - page 16

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 16 of 27 209-ball FBGA Boundary Scan Order [12, 13] CY7C1464A V25 (512K x 72) Bit# Ball ID Bit# Ball ID Bit# Ball ID Bit# Ball ID 1 W6 36 F6 71 H6 106 K3 2 V6 37 K8 72 C6 107 K4 3 U6 3 8 K9 73 B6 108 K6 4 W7 3 9 K10 74 A6 109 K2 5V 7 4 0 J 1 1 7 5 A 5 1 1 0 L 2 6 U7 41 J10 ...

  • Cypress CY7C1464AV25 - page 17

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 17 of 27 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... ............................ ...... ...

  • Cypress CY7C1464AV25 - page 18

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 18 of 27 Cap acit ance [16] Parameter Description T est Conditions 100 TQFP Max. 165 FBGA Max. 209 FBGA Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 2.5V V DDQ = 2.5V 6.5 7 5 pF C CLK Clock Input Capacitance 3 7 5 pF C I/O Input/Output Capacitance 5.5 6 ...

  • Cypress CY7C1464AV25 - page 19

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 19 of 27 Switching Characteristics Over the Operating Range [21, 22] Parameter Descriptio n –250 –200 –167 Unit Min. Max. Min. Max. Min. Max. t Power [17] V CC (typical) to the first access read or write 1 1 1 ms Clock t CYC Clock Cycle T ime 4.0 5.0 6.0 ns F MAX Max ...

  • Cypress CY7C1464AV25 - page 20

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 20 of 27 Switching W aveforms Read/Write/T iming [23, 2 4, 25] NOP , ST ALL and DESELECT Cycles [23, 24, 26] Notes: 23. For this waveform ZZ is tied low . 24. When CE is LOW , CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW . When CE is H IGH,CE 1 is HIGH o r CE 2 is LOW or CE ...

  • Cypress CY7C1464AV25 - page 21

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 21 of 27 ZZ Mode T iming [27, 28] Notes: 27. Device must be deselected when ente ring ZZ mode. See cycle descr iption t able for all possible signal condit ions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode . Switching W aveforms (continued) t Z ...

  • Cypress CY7C1464AV25 - page 22

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 22 of 27 Ordering Information Not all of the speed, package and temperature ranges ar e available. Please con t act your local sales repr esentative or visit www .cyp ress.com for a ctual produc ts offered. Spee d (MHz) Ordering Code Package Diagram Part and Package T ype ...

  • Cypress CY7C1464AV25 - page 23

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 23 of 27 250 CY7C1460A V25-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1462A V25-250AXC CY7C1460A V25-250BZC 51-85165 16 5-bal l Fine-P itch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1462A V25-250BZC CY7C1460A V25-250BZXC 51-85165 1 ...

  • Cypress CY7C1464AV25 - page 24

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 24 of 27 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE ...

  • Cypress CY7C1464AV25 - page 25

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 25 of 27 Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35 1.40 MAX. SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10.00 14.00 B C D E ...

  • Cypress CY7C1464AV25 - page 26

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 26 of 27 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodie ...

  • Cypress CY7C1464AV25 - page 27

    CY7C1460A V25 CY7C1462A V25 CY7C1464A V25 Document #: 38-05354 Rev . *D Page 27 of 27 Document History Page Document Title: CY7C146 0A V25/CY7C1462A V25/CY7C1464A V25 36 -Mbit (1-Mbit x 36/2-Mbit x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05354 REV . ECN No. Issue Date Orig. of Change Description of Change ** 25491 ...

Manufacturer Cypress Category Computer Hardware

Documents that we receive from a manufacturer of a Cypress CY7C1464AV25 can be divided into several groups. They are, among others:
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All of them are important, but the most important information from the point of view of use of the device are in the user manual Cypress CY7C1464AV25.

A group of documents referred to as user manuals is also divided into more specific types, such as: Installation manuals Cypress CY7C1464AV25, service manual, brief instructions and user manuals Cypress CY7C1464AV25. Depending on your needs, you should look for the document you need. In our website you can view the most popular manual of the product Cypress CY7C1464AV25.

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A complete Cypress manual, should contain several basic components. Some of them are less important, such as: cover / title page or copyright page. However, the remaining part should provide us with information that is important from the point of view of the user.

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2. Contents - index of all tips concerning the Cypress CY7C1464AV25, that we can find in the current document
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5. FAQ - Frequently Asked Questions
6. Contact detailsInformation about where to look for contact to the manufacturer/service of Cypress CY7C1464AV25 in a specific country, if it was not possible to solve the problem on our own.

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