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Manual Cypress Semiconductor CY7C1354CV25

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  • Cypress Semiconductor CY7C1354CV25 - page 1

    9-Mbit (256K x 36/512K x 18) Pi p elined SRAM with NoBL™ Architecture CY7C1354CV25 CY7C1356CV25 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05537 Rev . *H Revised September 14, 2006 Features • Pin-comp atible with and f unctionally e quivalent to ZBT™ • Supports 2 ...

  • Cypress Semiconductor CY7C1354CV25 - page 2

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 2 of 28 A0, A1, A C MODE BW a BW b WE CE1 CE2 CE3 OE READ LOGIC DQs DQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LO ...

  • Cypress Semiconductor CY7C1354CV25 - page 3

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 3 of 28 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQa DQa V DDQ V SS DQa DQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A CE 1 CE 2 BWa CE 3 V DD V SS CLK WE CEN O ...

  • Cypress Semiconductor CY7C1354CV25 - page 4

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 4 of 28 Pin Configurations (continued) 234 5 6 7 1 A B C D E F G H J K L M N P R T U DQ a V DDQ NC/576 M NC/1G DQ c DQ d DQ c DQ d AA A A NC/18M V DDQ CE 2 A V DDQ V DDQ V DDQ V DDQ NC/144 M NC A DQ c DQ c DQ d DQ d TMS V DD A NC/72M DQP d A A ADV/LD AC E 3 NC V DD AA N C V SS V SS NC DQP ...

  • Cypress Semiconductor CY7C1354CV25 - page 5

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 5 of 28 Pin Configurations (continued) 23 4 567 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/36M NC/72M V DDQ BW d BW a CLK WE V SS V SS V SS V SS V DDQ V SS V DD V SS V SS V SS ...

  • Cypress Semiconductor CY7C1354CV25 - page 6

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 6 of 28 Pin Definitions Pin Name I/O T ype Pin Description A0 A1 A Input- Synchronous Address Input s used to select one of the address loc atio ns . Sampled at the rising edge of the CLK. BW a, BW b, BW c, BW d, Input- Synchronous Byte Write Select Input s, active LOW . Qualified with WE ...

  • Cypress Semiconductor CY7C1354CV25 - page 7

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 7 of 28 Functional Overview The CY7C1354CV25 and CY7C1 356CV25 are synchronous-pipel ined Burst NoBL SRAMs designed specifi- cally to eliminate wait states during Write/Read transitions. All synchronous inp uts pass through input registers controlled by the rising edge of the clock. The c ...

  • Cypress Semiconductor CY7C1354CV25 - page 8

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 8 of 28 order to greatly simplify Read/Modi fy/Write sequences, which can be reduced to simpl e Byte Write operations. Because the CY7C1354CV25 and CY7C 1356CV25 are common I/O devices, data should not be driven into the device while the outputs are active. The Outpu t Enable (OE ) can be ...

  • Cypress Semiconductor CY7C1354CV25 - page 9

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 9 of 28 NOP/WRITE ABORT (Begin Burs t) None L L L L H X L L-H T ri-S tate WRITE ABORT (Continue Burst) Next X L H X H X L L-H T ri-S tate IGNORE CLOCK EDGE (S t all) Current X L X X X X H L-H – SLEEP MODE None X H X X X X X X T ri-St ate Partial Write Cycle Description [2, 3, 4, 9] Func ...

  • Cypress Semiconductor CY7C1354CV25 - page 10

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 10 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1354CV25/CY7C1356 CV 25 incorporates a serial boundary scan test access port (T AP) in the BGA package only . The TQFP package does not offer this functionality . Thi s part operates in accordance with IEEE S t andar d 1 149.1-190 ...

  • Cypress Semiconductor CY7C1354CV25 - page 11

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 1 1 of 28 It is also loaded with the IDCODE instruction if the con troller is placed in a re set state as described in the previous section. When the T AP controller i s in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault is ...

  • Cypress Semiconductor CY7C1354CV25 - page 12

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 12 of 28 TA P T i m i n g T AP AC Switching Characteristics Over the Operating Range [1 1, 12] Parameter Description Min. Max. Un it Clock t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH Time 20 ns t TL TCK Clock LOW Time 20 ns Output Times t TDOV TCK ...

  • Cypress Semiconductor CY7C1354CV25 - page 13

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 13 of 28 2.5V T AP AC T est Conditions Input pulse levels .. ......... ...... ........... ........... ........ V SS to 2.5V Input rise and fall time .......... .............. ........... ... ........... ... 1 ns Input timing referenc e levels ................... ........... .......... 1.2 ...

  • Cypress Semiconductor CY7C1354CV25 - page 14

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 14 of 28 Boundary Scan Exit Order (256K × 36) Bit # 1 19-ball ID 165-ball ID 1K 4 B 6 2H 4 B 7 3M 4 A 7 4F 4 B 8 5B 4 A 8 6G 4 A 9 7C 3 B 1 0 8B 3 A 1 0 9D 6 C 1 1 10 H7 E10 11 G 6 F 1 0 12 E6 G10 13 D7 D10 14 E7 D1 1 15 F6 E1 1 16 G7 F1 1 17 H6 G1 1 18 T7 H1 1 19 K7 J10 20 L6 K10 21 N6 ...

  • Cypress Semiconductor CY7C1354CV25 - page 15

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 15 of 28 Boundary Scan Exit Order (512K × 18) Bit # 1 1 9-ball ID 165-ball ID 1K 4 B 6 2H 4 B 7 3M 4 A 7 4F 4 B 8 5B 4 A 8 6G 4 A 9 7C 3 B 1 0 8B 3 A 1 0 9T 2 A 1 1 10 Not Bonded (Preset to 0) Not Bonded (Preset to 0) 1 1 Not Bonded (Preset to 0) Not Bonded (Preset to 0) 12 Not Bonded (P ...

  • Cypress Semiconductor CY7C1354CV25 - page 16

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 16 of 28 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T e mperature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... ............................ ...... –55°C to +12 ...

  • Cypress Semiconductor CY7C1354CV25 - page 17

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 17 of 28 Cap acit ance [16] Parameter Description T est Conditions 100 TQFP Max. 1 19 BGA Max. 165 FBGA Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 2.5V , V DDQ = 2.5V 555 p F C CLK Clock Input Capacitance 5 5 5 pF C I/O Input/Output Capacitance 5 7 7 pF Thermal Resist ...

  • Cypress Semiconductor CY7C1354CV25 - page 18

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 18 of 28 Switching Characteristics Over the Operating Range [18, 19] Parameter Descriptio n –250 –200 –166 Unit Min. Max. Min. Max. Min. Max. t Power [17] V CC (typical) to the First Access Read or Write 1 1 1 ms Clock t CYC Clock Cycle T ime 4.0 5 6 ns F MAX Maximum Operating Frequ ...

  • Cypress Semiconductor CY7C1354CV25 - page 19

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 19 of 28 Switching W aveforms Read/Write T iming [23, 24, 25] Notes: 23. For this waveform ZZ is tied LOW. 24. When CE is LOW, CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW . When CE is H IGH,CE 1 is HIGH o r CE 2 is LOW or CE 3 is HIGH. 25. Order of the Burst sequence is determined by the s ...

  • Cypress Semiconductor CY7C1354CV25 - page 20

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 20 of 28 NOP , ST ALL and DESELECT CYCLES [23, 24, 26] Note: 26. The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrated CEN being used to create a pause. A wr ite is not perform ed during this cycle. Switching W aveforms (continued) READ Q(A3) 456789 1 0 CLK CE WE CEN BW X ADV/LD ADD ...

  • Cypress Semiconductor CY7C1354CV25 - page 21

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 21 of 28 ZZ Mode T iming [27, 28] Notes: 27. Device must be deselected when entering ZZ mode. See cycle descr ipt ion table for all possible signal conditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode. Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ...

  • Cypress Semiconductor CY7C1354CV25 - page 22

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 22 of 28 Ordering Information Not all of the speed, package and temperature ranges ar e ava ilable. Please contact your local sales representative or visit www .cypress.com for actual products offered. Speed (MHz) Orderi ng Code Package Diagram Part and Package T ype Operating Range 166 C ...

  • Cypress Semiconductor CY7C1354CV25 - page 23

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 23 of 28 200 CY7C1354CV25-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1356CV25-200AXC CY7C1354CV25-200BGC 51-851 1 5 1 19-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1356CV25-200BGC CY7C1354CV25-200BGXC 51-851 1 5 1 19-ball Ball Grid Array (14 x ...

  • Cypress Semiconductor CY7C1354CV25 - page 24

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 24 of 28 250 CY7C1354CV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1356CV25-250AXC CY7C1354CV25-250BGC 51-851 1 5 1 19-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1356CV25-250BGC CY7C1354CV25-250BGXC 51-851 1 5 1 19-ball Ball Grid Array (14 x ...

  • Cypress Semiconductor CY7C1354CV25 - page 25

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 25 of 28 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD ...

  • Cypress Semiconductor CY7C1354CV25 - page 26

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 26 of 28 Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF. U T R P N M L K J H G F E D C A B 21 43 65 7 Ø1.00(3X) REF. 7.62 22.00±0.20 14.00±0.20 1.27 0.60±0.10 C 0.15 C B A 0.15(4X) Ø0.05 M C Ø0 ...

  • Cypress Semiconductor CY7C1354CV25 - page 27

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 27 of 28 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress ...

  • Cypress Semiconductor CY7C1354CV25 - page 28

    CY7C1354CV25 CY7C1356CV25 Document #: 38-05537 Rev . *H Page 28 of 28 Document History Page Document Title: CY7C1354CV25/CY7C1356CV25 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoB L™ Architecture Document Number: 38-05537 REV . ECN No. Issue Date Orig. of Change Description of Ch a ng e ** 242032 See ECN RKF New data sheet *A 278969 See EC ...

Manufacturer Cypress Semiconductor Category Computer Hardware

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All of them are important, but the most important information from the point of view of use of the device are in the user manual Cypress Semiconductor CY7C1354CV25.

A group of documents referred to as user manuals is also divided into more specific types, such as: Installation manuals Cypress Semiconductor CY7C1354CV25, service manual, brief instructions and user manuals Cypress Semiconductor CY7C1354CV25. Depending on your needs, you should look for the document you need. In our website you can view the most popular manual of the product Cypress Semiconductor CY7C1354CV25.

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