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Manual Xilinx 3.2

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  • Xilinx 3.2 - page 1

    LogiCORE™ IP CAN v3.2 Getting Star ted Guide UG186 April 19, 2010 ...

  • Xilinx 3.2 - page 2

    CAN Getting Started Guide www .xilinx.com UG186 Apr il 19, 2010 Xilinx is providing this product documentation, hereinafter “Inf or mation, ” to you “AS IS” with no warr anty o f an y kind, express or implied. Xilinx makes no represen tation that the Inf or mation, or an y p ar t icular implementation thereo f, is free from any claims of in ...

  • Xilinx 3.2 - page 3

    CAN Getting Started Guide www .xilinx.com 3 UG186 Apr il 19, 2010 Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx 3.2 - page 4

    4 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design Directory and File Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 <project directory> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Xilinx 3.2 - page 5

    CAN Getting Started Guide www .xilinx.com 5 UG186 Apr il 19, 2010 Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Quick Start Example Design Figure 3-1: Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3-2: CAN Main Screen . . . . . . . . . . . . . . . ...

  • Xilinx 3.2 - page 6

    6 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 ...

  • Xilinx 3.2 - page 7

    CAN Getting Started Guide www .xilinx.com 7 UG186 Apr il 19, 2010 Pr eface About This Guide The CAN v3.2 Getting Started Guide provides information about generating the LogiCORE™ IP CAN core, customizing and si mulating the cor e with the provide d example design, and r unning the design files thr ough implementation us ing the Xilinx tools. Guid ...

  • Xilinx 3.2 - page 8

    8 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Pref ace: About This Guide Online Document The following li nking conventi ons ar e used in this document: Italic font V ariables in a s yntax statement for which you must supply values ngdbuild design_name References to other manuals See the User Guide for details. Emphasis in text ...

  • Xilinx 3.2 - page 9

    CAN Getting Started Guide www .xilinx.com 9 UG186 Apr il 19, 2010 Chapter 1 Intr oduction The LogiCORE™ IP CAN v3. 2 core is a compact, full-featur ed targeted design platform that conforms to ISO 1 1898-1 , CAN2.0A and CAN2.0B standards. Bit rates of up to 1 M bps are suppor ted. The core size can be optimi zed using parameterized configurations ...

  • Xilinx 3.2 - page 10

    10 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 1: Introd uction Recommended Design Experience Although the CAN core is a fully-veri fied targ eted design platform, the challenge associated with implementing a complete CAN design vari es, depending on the application requir ements. For best results, pr evious experience w ...

  • Xilinx 3.2 - page 11

    CAN Getting Started Guide www .xilinx.com 11 UG186 Apr il 19, 2010 Chapter 2 Licensing the Cor e This chapter provides instructions for obtaining a license for the CAN core, which you mu s t d o be f ore u si n g t h e c ore i n y o ur d es i gn s . T h e C A N co re is p rov id e d un d er t he te r ms of the Xilinx LogiCORE Site License Ag reeme ...

  • Xilinx 3.2 - page 12

    12 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 2: Licensing the Core Full The Full license k ey is available when y ou pur chase the cor e and provides full acce ss to all core f unctionality both in si mulation and in har dware, i ncluding: • Gate-level functional simulation support • Back annotated gate-level simul ...

  • Xilinx 3.2 - page 13

    CAN Getting Started Guide www .xilinx.com 13 UG186 Apr il 19, 2010 Chapter 3 Quick Start Example Design This chapter pr ovides instructions to gene rate a CAN core quickly , run the design thr ough implementation with the Xilinx tools, and si mulate the example design using the provided demonstration test bench. See th e example design in Chapter 4 ...

  • Xilinx 3.2 - page 14

    14 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 3: Quic k Start Example Design Generating the Core This section describes how to generate a CAN core with default values using the Xilinx CORE Generator™ tool. T o generate the core : 1. Start the CORE Generator tool. For help starting and using the CORE Generator tool, se ...

  • Xilinx 3.2 - page 15

    CAN Getting Started Guide www .xilinx.com 15 UG186 Apr il 19, 2010 Implementing th e Example Design 7. In the Component Name field , enter a name for the cor e instance. This example uses the name quickstart . 8. After selecting the parameters from the GUI screens, click Finish. The core and its supporting files, includ in g the example design, are ...

  • Xilinx 3.2 - page 16

    16 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 3: Quic k Start Example Design Functional Simulation This section provide s instructions for running a functional simulation of the CAN core using either VHDL or V erilog. Functional simulation models ar e provided when the cor e is generated. Implementing the core befor e s ...

  • Xilinx 3.2 - page 17

    CAN Getting Started Guide www .xilinx.com 17 UG186 Apr il 19, 2010 Chapter 4 Detailed Example Design This chapter provides detailed information about the example design, including a description of fil es and the dir ectory structur e gene rated by the Xilinx CORE Generator™ software, the purpose and contents of the pr ov ided scripts, the content ...

  • Xilinx 3.2 - page 18

    18 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design Directory and File Contents The CAN v3.2 core dir ectories and their asso ciated files are defined in the following sections. <project director y> The <project dir ectory> contains all the CORE Generator software pr oject files. <pro ...

  • Xilinx 3.2 - page 19

    CAN Getting Started Guide www .xilinx.com 19 UG186 Apr il 19, 2010 Directory and File Contents <component_name>e xample design The example design dir ectory contains the ex ample design files pr ovided with the core. <component_name>/doc The doc directory contains the PDF documentation provided with the core . T able 4-3: Example Desig ...

  • Xilinx 3.2 - page 20

    20 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design <component_name>/implement The implement directory contains the core impl ementation script fi les. Generated for Full- Sy s te m Ha rd w are E va l ua t io n an d F ul l l ic en s e ty p es . <component_name>/implement/results The resu ...

  • Xilinx 3.2 - page 21

    CAN Getting Started Guide www .xilinx.com 21 UG186 Apr il 19, 2010 Directory and File Contents <component_name>/sim ulation/functional The functional directory contains functional simulation scripts pr ovided with the core. T able 4-8: Functional Director y Name Description <project_dir>/<component_n ame>/sim ulation/functional si ...

  • Xilinx 3.2 - page 22

    22 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design simulation/timing The timing simulation directory is generated only for Full-System Hardware Evaluation and Full-license ty pes. T able 4-9: Timing Directory Name Description <project_dir>/<component_name>/sim ulation/timing simulate_mt ...

  • Xilinx 3.2 - page 23

    CAN Getting Started Guide www .xilinx.com 23 UG186 Apr il 19, 2010 Implementati on Scripts Implementation Scripts Note: Present only with a Full license. The implementation script is either a shell scri pt(.s h) or batch file (. bat) that pr ocesses the example design through the Xilinx tool flow . It is located at: Linux <project_dir>/<co ...

  • Xilinx 3.2 - page 24

    24 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design Timing Simulation Note: Present only with a Full license. The test scripts ar e a ModelSim or a Cadence IES macro that automates the simulation of the test bench. They are located in: <project_dir>/<component_name>/simul ation/timing/ T ...

  • Xilinx 3.2 - page 25

    CAN Getting Started Guide www .xilinx.com 25 UG186 Apr il 19, 2010 Demonstration T est Benc h Demonstration T est Bench Figur e 4-2 illustrates the demonstration test be nch. T est Bench Functionality The demonstration test bench is a straightforw ard VHDL or V erilog file to exer cise the example design and the core itself. The test bench consists ...

  • Xilinx 3.2 - page 26

    26 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design • Five messages are written in seque nce: 1. The first message is written to the TXHPB and is a standar d data frame. 2. The second messag e is written t o the TX FIFO a nd is a stand ar d data frame. 3. The third message is written to the TX FIF ...

  • Xilinx 3.2 - page 27

    CAN Getting Started Guide www .xilinx.com 27 UG186 Apr il 19, 2010 Demonstration T est Benc h • After the fourth message is transmitted and received, the Interrupt Enable Register is written to enable interr upts for TXOK, RXOK and TXBFLL. This regis t er is re ad fr om and the value r ead is compar ed with the value written. • The fifth messag ...

  • Xilinx 3.2 - page 28

    28 www .xilinx.com CAN Getting Started Guide UG186 Apr il 19, 2010 Chapter 4: Detailed Example Design ...

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