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Cypress CY7C1245V18 - page 1
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 36-Mbit QDR™-II+ SRAM 4-W ord Burst Architecture (2.0 Cycle Read Latency) Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-06365 Rev . *D Revised March 12, 2008 Features ■ Separate independent read and write data ports ? ...
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Cypress CY7C1245V18 - page 2
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 2 of 28 Logic Block Diagram (CY7C1241V18) Logic Block Diagram (CY7C1256V18) 1M x 8 Array CLK A (19:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg. RPS WPS Q [7:0] Control Logic Address Register Reg. Reg. Reg. 16 20 8 32 8 NW ...
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Cypress CY7C1245V18 - page 3
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 3 of 28 Logic Block Diagram (CY7C1243V18) Logic Block Diagram (CY7C1245V18) 512K x 18 Array CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Q [17:0] Control Logic Address Register Reg. Reg. Reg. 36 19 18 7 ...
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Cypress CY7C1245V18 - page 4
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 4 of 28 Pin Configurations CY7C1241V18 ( 4M x 8) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 23 4 5 6 7 1 A B C D E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/72M A NWS 1 K WPS NC/144M NC NC NC NC NC TDO NC NC D5 NC NC NC TCK NC NC A NC/288M K NWS 0 V SS AN ...
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Cypress CY7C1245V18 - page 5
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 5 of 28 Pin Configurations (continued) CY7C1243V18 ( 2M x 18) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 23 4 56 7 1 A B C D E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/14 4M A BWS 1 K WPS NC/288M Q9 D9 NC NC NC TDO NC NC D13 NC NC NC TCK NC D10 A NC K BWS ...
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Cypress CY7C1245V18 - page 6
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 6 of 28 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks during valid write operations. CY7C1241V18 − D [7: 0] CY7C1256V18 − D [8: 0] CY7C1243V18 − D [17:0] CY7C1245 ...
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Cypress CY7C1245V18 - page 7
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 7 of 28 CQ Echo Clock Synchronou s Ec ho Clock Outpu ts . This is a free running clock and is synchronized to the input clock (K) of the QD R-II+. The timing for the echo clocks is shown in “Switching Character- istics” on page 23 . CQ Echo Clock Synchron ...
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Cypress CY7C1245V18 - page 8
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 8 of 28 Functional Overview The CY7C1241V18, CY7C1256 V18, CY7C1243V18, and CY7C1245V18 are synch ronous pipelined Burst SRAMs equipped with a rea d and a write port. The read port is dedicated to read operations and the write port is dedicated to write opera ...
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Cypress CY7C1245V18 - page 9
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 9 of 28 Depth Exp ansion The CY7C1243V18 has a Po rt Select input for each port. T his enables easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. ...
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Cypress CY7C1245V18 - page 10
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 10 of 28 Application Example Figure 1 shows the use of 4 QDR-II+ SRAMs in an application. Figure 1. Appl ic ation Example T ruth T able The truth table for the CY7C1241V18, CY7C1256V 18, CY7C1243V1 8, and CY7C1 245V18 follows. [2, 3, 4, 5, 6, 7] Operation K R ...
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Cypress CY7C1245V18 - page 11
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 1 1 of 28 Write Cycle Descriptions The write cycle description table for CY7C1241V18 and CY7C1243V18 follows. [2, 10] BWS 0 / NWS 0 BWS 1 / NWS 1 K K Comments L L L–H – During the data portion of a write sequence : CY7C1241V18 − both ni bbles (D [7:0] ) ...
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Cypress CY7C1245V18 - page 12
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 12 of 28 Write Cycle Descriptions The write cycle description ta ble for CY7C1245V18 follows. [2, 10] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments LLLL L – H – D u r i n g t h e d a t a p o r t i o n o f a w r i t e s e q u e n c e , a l l f o u r b y t e s ( D [ ...
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Cypress CY7C1245V18 - page 13
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 13 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan test access port (T AP) in the FBGA package. This part is fully compliant with IEEE S tandard #1 149. 1-2001. The T AP operates using JEDEC standard 1.8V IO logi ...
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Cypress CY7C1245V18 - page 14
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 14 of 28 IDCODE The IDCODE instruction loads a vendor-sp ecific, 32-bit code into the instruction register . It also places the in struction register between the TDI and TDO pins an d shifts the IDCODE out of the device when the T AP controller enters the Shi ...
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Cypress CY7C1245V18 - page 15
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 15 of 28 T AP Controller St ate Diagram The state diagram for the CY7C124 1V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 follo ws. [1 1] TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR SELECT IR- ...
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Cypress CY7C1245V18 - page 16
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 16 of 28 T AP Controller Block Diagram T AP Electrical Ch aracteristics Over the Operating Range [12, 13, 14 ] Parameter Descriptio n T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 μ ...
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Cypress CY7C1245V18 - page 17
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 17 of 28 T AP AC Switchi ng Characteristics Over the Operating Range [15, 16 ] Parameter Descriptio n Min Max Unit t TCYC TCK Clock Cycle T ime 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Set ...
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Cypress CY7C1245V18 - page 18
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 18 of 28 Identification Register Definitions Instruction Field Va l u e Description CY7C1241V18 CY7C1256V18 CY7C1 243V18 CY7C1245V18 Revision Number (31:29) 000 000 000 0 00 V ersion numb er . Cypress Device ID (28:12) 1 10100101010001 1 1 1 1010010101001 1 1 ...
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Cypress CY7C1245V18 - page 19
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 19 of 28 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6 P2 9 9 G 5 7 5 B8 5 2 J 2 6N 30 1 1F 58 5A 86 3K 3 7P 31 1 1G 59 4A 87 3J 4 7 N3 2 9 F 6 0 5 C8 8 2 K 5 7R 33 10F 61 4B 89 1K 6 8R 34 1 1E 62 3A 9 ...
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Cypress CY7C1245V18 - page 20
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 20 of 28 Power Up Sequence in QDR-II+ SRAM QDR-II+ SRAMs must be powered up and ini tialized in a predefined manner to prevent undefined opera tions. During power up, when the DOFF is tied HIGH, the DLL is locked after 2048 cycles of stable clock. Power Up Se ...
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Cypress CY7C1245V18 - page 21
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 21 of 28 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User gui d el i ne s are not tested. S t orage T emperature ................ .............. ... –65°C to +150°C Ambient T emperature with Powe r Applied .. –55 ...
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Cypress CY7C1245V18 - page 22
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 22 of 28 Cap acita nce T ested initially and after any design or proc ess change that may affect these parameters. Parameter Descriptio n T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V V DDQ = 1.5V 5p F C CLK Clock Inpu ...
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Cypress CY7C1245V18 - page 23
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 23 of 28 Switching Characteristics Over the Operating Range [22, 23] Cypress Parameter Consortium Parameter Description 375 MH z 333 MHz 300 MHz Unit Min Max Min Max Min Max t POWER V DD (T ypical) to the First Access [24] 1–1–1– m s t CYC t KHKH K Cloc ...
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Cypress CY7C1245V18 - page 24
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 24 of 28 Switching W aveforms Figure 4. Read/Write/Deselect Sequence wave form for 2.0 Cycle Read Latency [30, 31, 32] t KH t KL t CYC t KHKH NOP READ NOP WRITE READ WRITE 1 23 4 5 6 7 8 t t t t SA HA SC HC t HD t SC t HC A0 A1 A2 A3 t t SD HD t SD D1 1 D10 D ...
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Cypress CY7C1245V18 - page 25
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 25 of 28 Ordering Information Not all of the speed, package and temperat ure ranges are avail able. Please contact your local sales representative or visit www .cypress.com for actual produ cts offered. Speed (MHz) Ordering Co de Package Diagram Package T ype ...
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Cypress CY7C1245V18 - page 26
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 26 of 28 300 CY7C1241V18-300 BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1256V18-300BZC CY7C1243V18-300BZC CY7C1245V18-300BZC CY7C1241V18-300BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY ...
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Cypress CY7C1245V18 - page 27
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Document Number: 001-06365 Rev . *D Page 27 of 28 Package Diagram Figure 5. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 ! 0).#/2.%2 ¼ ¼ ...
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Cypress CY7C1245V18 - page 28
Document Number: 001-06365 Rev . *D Revised March 12, 2008 Page 28 of 28 QDR™ is a trademark of Cypress Semicond uctor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of prod ucts developed by Cypress, IDT , NEC, Renesas, and Sam sung. All product an d c ompany names me ntioned in t his document are the trad emarks of th eir respe c ...
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