English dropdown-ico

Manual Analog Devices AD9912

40 pages 1.05 mb
Download

Go to site of 40

Summary
  • Analog Devices AD9912 - page 1

    1 GSPS Direct Digi tal Synthesizer with 14 - Bit DAC AD9912 Rev. D Info rmation fu rnished by A nalog Devic es is believed to be ac curate an d reliable . Ho wev er , no respo nsibility is assumed by An alog Devices fo r its use, nor for any infringements of p atents or other rights of third parties that may resu lt from its use . Specif ications s ...

  • Analog Devices AD9912 - page 2

    AD9912 Rev. D | Page 2 of 40 T ABLE OF CONTENTS Fea tures .............................................................................................. 1  A pplica tions ....................................................................................... 1  General Descr iption ............................................................. ...

  • Analog Devices AD9912 - page 3

    AD9912 Rev. D | P age 3 of 40 SPECIFICA TIONS DC SPE CIFICATI ONS A VDD = 1.8 V ± 5% , A V DD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5% , A VSS = 0 V , D VS S = 0 V , u nless o therwise noted. Tabl e 1 . Paramet er Min Ty p Max Uni t T est Conditio ns/ Co mments SUPPL Y VOL T AGE DVDD_I/O (Pin 1) 3.135 3. 30 3.465 V DVD D ( Pin 3, ...

  • Analog Devices AD9912 - page 4

    AD9912 Rev. D | P age 4 of 40 Paramet er Min Ty p Max Uni t T est Conditio ns/ Co mments SYSTEM CLOCK INPU T Syste m clock in puts sho uld alwa ys be ac - coupl ed (b oth s ingl e - ended and diff erentia l) SYSCLK PLL Bypas sed In put Capaci tance 1.5 pF Sing le - ended, ea ch pin Input Resistan ce 2.4 2.6 2.9 kΩ Differ entia l Interna lly Gene ...

  • Analog Devices AD9912 - page 5

    AD9912 Rev. D | P age 5 of 40 AC SPECIFI CATIONS f S = 1 GHz, DA C R SET = 10 k Ω , u nless otherwis e noted . P ower suppl y pins within the range sp ecif ied in the DC Spec ifications se ctio n. Table 2 . Paramet er M in Typ Max Un it Test Conditions/Comments FDBK _IN I NPU T Pin 40, Pin 41 Input F reque ncy Range 10 400 MHz Minim um Diffe renti ...

  • Analog Devices AD9912 - page 6

    AD9912 Rev. D | P age 6 of 40 Paramet er M in Typ Max Un it Test Conditions/Comments CMOS Output Driver (AVDD3/Pi n 37) @ 1. 8 V Freq uency Ra nge 0.008 40 MHz See Figur e 28 f or maximum togg le rate Duty Cyc le 45 55 65 % With 20 pF load and up to 40 MHz Rise Time /Fall Ti me (20% to 80% ) 5 6.8 ns With 20 pF load DAC OUTPUT CHARAC TERISTICS DCO ...

  • Analog Devices AD9912 - page 7

    AD9912 Rev. D | P age 7 of 40 ABSOLUTE MAXIMUM RA T INGS Table 3. Paramet er Rating Analog Su pply V oltag e (A VDD) 2 V Digital Su pply Voltag e (DVDD ) 2 V Digital I/ O Supply Vo ltage (DVDD_I/O) 3.6 V DA C Supply Voltage ( A VDD3 Pin s ) 3.6 V Maximu m Digital I nput V oltage −0.5 V to D VDD_ I/O + 0. 5 V Storag e T e mpera ture −65°C t o + ...

  • Analog Devices AD9912 - page 8

    AD9912 Rev. D | P age 8 of 40 PIN CONFIGURA TION AND FUNCTION DE SCRIPTI ONS PIN 1 INDI C A T OR 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC NC A V DD NC NC NC A V DD A V DD A V DD A V DD SYSCLK SYSCLKB A V DD A V DD LOOP_ FI L T ER CLKM ODES E L 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SCL K SDI O SDO CSB IO _UPD A TE RESET PW RDOW N ...

  • Analog Devices AD9912 - page 9

    AD9912 Rev. D | P age 9 of 40 P i n N o. Input / Output P i n Ty p e Mnemonic Descriptio n 32 I 1.8 V CMO S CLK MODE SEL Clock Mode Selec t. Set to GND whe n connecting a cr ystal to the system clock inp ut (P in 27 and P in 28). P ull up to 1.8 V whe n using ei ther an oscillator or an external cloc k sourc e . This pin c an be l eft uncon nected ...

  • Analog Devices AD9912 - page 10

    AD9912 Rev. D | P age 10 of 40 TYPICAL PERFORMA NCE CHARACTERIST ICS AV D D , AV D D 3 , a n d D VDD a t nominal supp ly vol tage; DAC R SET = 10 k Ω, unless otherwis e noted. See Fig ure 26 for 1 GHz re fe re nce pha s e n oi se used for gen era ting these p lo ts . 06763-003 0 100 200 300 400 500 OUT PUT F REQ UE NCY ( M Hz) –50 –55 –60 ? ...

  • Analog Devices AD9912 - page 11

    AD9912 Rev. D | P age 11 of 40 06763-009 19.85 19. 95 20. 05 20.15 20.25 20. 35 FREQUENCY (MH z) 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 SI G NAL P O W E R ( d Bm) 20.1M Hz –95dBc 500kHz 300Hz 1kHz CARRIE R: SF DR: FRE Q . S P AN: RE SOLUTION BW: VI DE O BW: Figure 9 . Narrow -B and SFDR at 20.1 MHz , SYSCLK = 1 G ...

  • Analog Devices AD9912 - page 12

    AD9912 Rev. D | P age 12 of 40 06763-015 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) –100 –110 –120 –130 –140 –150 PHASE N OISE (d Bc/Hz) 800MHz 600MHz RMS JI TT ER (100Hz T O 100M Hz) : 600MHz: 800MHz: 585fs 406fs Figure 15 . Absolute Phase Noise U sing H STL Driver , SYSCLK = 1 GHz Wenzel Oscilla tor ( SYSCLK PLL By pass ed) , H ...

  • Analog Devices AD9912 - page 13

    AD9912 Rev. D | P age 13 of 40 06763-051 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) –125 –115 –135 –145 –155 –165 –175 PHASE N OISE (d Bc/Hz) RMS JI TT ER (100Hz T O 20M Hz) : 50MHz: 200MHz: 400MHz: 62fs 37fs 31fs 200MHz 400MHz 50MHz Figure 21 . Absolute Phase Noise of U nfiltered DAC Output , f OUT = 50 MHz, 200 MH z, and 400 ...

  • Analog Devices AD9912 - page 14

    AD9912 Rev. D | P age 14 of 40 06763-021 0 200 400 600 800 FREQUENCY (MH z) 650 600 550 500 450 AMPLITUDE (mV) NOM S KE W 25°C, 1. 8V S UP P L Y WORST CASE (SLOW SKEW 90°C, 1.7V SUPPLY) Figure 27 . HSTL Out pu t Driver Single - En ded Peak -to- Pe ak Amplitud e vs. Toggle Rate (100 Ω Across Differential P air) 06763-022 0 10 20 30 40 FREQUENCY ( ...

  • Analog Devices AD9912 - page 15

    AD9912 Rev. D | P age 15 of 40 INPUT/OUTPUT TER MINA TION RECOMM EN DA TIONS DOW NST REAM DEVI CE (H IGH-Z) AD9912 1.8V HST L OUT PUT 100 Ω 06763-027 0.01µ F 0.01µ F Figure 33 . AC - Coupled HST L Output Driver DOW NST REAM DEVI CE (H IGH-Z) AD9912 1.8V HST L OUT PUT 50 Ω 50 Ω 06763-028 AVDD/ 2 Figure 34 . DC - Coupled HST L Output Driver A ...

  • Analog Devices AD9912 - page 16

    AD9912 Rev. D | P age 16 of 40 THEOR Y OF OPERA TION 06763-031 DDS/ DAC FRE QUENCY TUNI NG W O RD ÷S 2× DIGI TAL SY NTHES IS CORE CONT ROL LOGIC LOW NOIS E CLO CK MU LTIPLIER AMP SYSCLK PORT EXT ERNAL ANALO G LOW -PASS FILTER EXT ERNAL LOOP FILTER DIGITA L INT ERF ACE SYSCLK SYSCLKB S1 TO S4 FDBK_I N FDBK_I NB DAC_OUT DAC_OUT B OUT OUTB OUT _CMO ...

  • Analog Devices AD9912 - page 17

    AD9912 Rev. D | P age 17 of 40 06763-032 DAC (14-BI T) AN GLE TO AMPL IT UDE CONVE RSI ON 14 19 19 48 48 48 14 PHASE OFFSET Q D 48-BIT ACCUMUL ATO R FREQ UENCY TUNI NG W O RD (FTW) f S DAC_RSET DAC_OUT DAC_OUT B DAC I-S E T REGISTERS AN D LOGIC Figure 40 . DDS Block Diagram The inp ut to the DDS is a 4 8- bit FT W that pro vides the accu - m ula to ...

  • Analog Devices AD9912 - page 18

    AD9912 Rev. D | P age 18 of 40 PRI MARY SI GNAL FILTER RESPONSE SIN(x)/x ENVELOPE SPURS IMAGE 0 IMAGE 1 IMAGE 2 IMAGE 3 IMAGE 4 0 –20 –40 –60 –80 –100 MAG NIT UDE (d B) f s /2 f s 3 f s /2 2 f s 5 f s /2 f BASE BAND 06763-034 Figure 42 . DAC Spectrum vs. Recons truction Filter R esponse Be ca use the D AC con stitu tes a samp led system, ...

  • Analog Devices AD9912 - page 19

    AD9912 Rev. D | P age 19 of 40 SYSC LK INPUTS Funct i onal D escription A n exter nal ti me base connects to the AD9912 at the SY SCLK pins t o genera te the in ternal hig h frequenc y system clock (f S ). The S Y SCLK in pu ts can be o perated i n on e of the following thr ee modes: • S Y SCLK P LL byp assed • S Y SCLK P LL ena bled w ith inpu ...

  • Analog Devices AD9912 - page 20

    AD9912 Rev. D | P age 20 of 40 SYSCLK PLL Multiplier When the SY SCLK PLL multiplier path is employ ed, the freq uency a pp lied to t he S Y SCLK inp ut pin s m ust be limi ted so as n ot t o ex ceed the maxi mu m in pu t freq uency of the S Y SCLK PLL p hase detecto r . A block di agram of th e SY SCLK gener at or app e ars i n Fig u re 45 . 06763 ...

  • Analog Devices AD9912 - page 21

    AD9912 Rev. D | P age 21 of 40 N ote t ha t the SY SCLK PLL b ypassed a nd S Y SCLK P LL ena bl ed input pat hs a re in te rna lly biase d to a d c level of ~1 V . Care should be taken to ensure that an y external connections do not disturb the dc bias be cause this may sign ifica ntl y degra de perform ance. Gener ally , it i s recommend ed that t ...

  • Analog Devices AD9912 - page 22

    AD9912 Rev. D | P age 22 of 40 Although the worst spurs tend to be harmonic in origin , the fact that the D AC is part of a sampled system results in the poss ibility of sp urs ap pearing in the outp ut spec tru m that are not harmoni - cally r elated to t he fundamen tal. F or exam ple, if the DA C is sampled at 1 GH z and ge ner ates an output si ...

  • Analog Devices AD9912 - page 23

    AD9912 Rev. D | P age 23 of 40 THERMAL PERFOR MANCE Table 7 . Thermal Paramete rs Symbo l Therm al Char acterist ic Us ing a JE DEC51 - 7 Plus JE DEC51 - 5 2S 2P T est B oard Valu e Unit θ JA Ju nc t i on - to - ambient t hermal r esistance , 0.0 m/s ec a ir flow per JE DEC JESD51 - 2 (still ai r) 25.2 °C/W θ JMA Jun c ti on - to - ambient ther ...

  • Analog Devices AD9912 - page 24

    AD9912 Rev. D | P age 24 of 40 POWER-UP POWER - ON RESET On initial power - up, t h e AD991 2 in terna lly genera tes a 75 ns RESET pulse. The puls e is initiated when b oth o f the following two condition s are met: • The 3.3 V supp ly is gr eater than 2.35 V ± 0.1 V . • The 1.8 V supp ly is gr eater than 1.4 V ± 0.05 V . Less than 1 ns afte ...

  • Analog Devices AD9912 - page 25

    AD9912 Rev. D | P age 25 of 40 POWER SUPPL Y PAR TITI ONING The AD9912 feat ures m ultiple pow er supp lies, and their power consum ption varies with its configuration. This s ection covers which power supp lies can be grouped together and how the powe r cons u mpti on of each blo ck v ar ies with f requency . The numbers quoted he re are for com p ...

  • Analog Devices AD9912 - page 26

    AD9912 Rev. D | P age 26 of 40 SERIAL CONTROL PORT The AD9912 se rial contr ol port is a flexible, synchro nous, serial co m m unications port that allows an easy interface with many indus tr y - standard microcon trollers and micr op rocessors. Single or m ultip le byte transf ers are su pported, as well as MSB first o r LSB first t ransfer forma ...

  • Analog Devices AD9912 - page 27

    AD9912 Rev. D | P age 27 of 40 Read If the instr ucti on wor d is for a rea d operation (I15 = 1), the next N × 8 SCLK cy cles c lock ou t the da ta from t he address specified in the instruction word, where N is 1, 2, 3, or 4, as deter mined by [ W1:W0 ] . In this case, 4 is used for str eaming m ode where fou r or mor e words a r e transf erred ...

  • Analog Devices AD9912 - page 28

    AD9912 Rev. D | P age 28 of 40 Table 10 . Serial Control Port, 16 - Bit Instr uction Word , MSB F irst MSB LS B I15 I14 I13 I 12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 R/ W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 06763-043 CSB SCLK DON' T CARE SDIO A12 W0 W1 R/W A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D ...

  • Analog Devices AD9912 - page 29

    AD9912 Rev. D | P age 29 of 40 06763-048 CSB SCL K SDI O t H IGH t LOW t CLK t S t DS t DH t H BIT N BIT N + 1 Figure 56 . Serial Co ntrol Port Timing — Write Table 11 . De finit ions o f Ter ms Used in Seria l Cont rol Port Tim ing Diagr ams Paramet er Descrip tion t CLK P eriod of SCLK t DV Rea d dat a valid time (t ime fro m f allin g edge of ...

  • Analog Devices AD9912 - page 30

    AD9912 Rev. D | P age 30 of 40 I/O REGISTER MAP All address and bi t location s that ar e left blank in Ta b l e 12 ar e unu sed . Table 12 . Addr (Hex) Type 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default (Hex) Serial port con figuration and pa rt i dentification 0x0000 Serial c onfi g. SDO a ctive LSB f ir st (buff ered) Soft r ese ...

  • Analog Devices AD9912 - page 31

    AD9912 Rev. D | P age 31 of 40 Addr (Hex) Type 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default (Hex) Calibration (user - acc essibl e t rim) 0x0400 to 0x040A Reserv ed 0x00 0x040B DAC full- scale c urrent DAC full -s cale c urrent , Bits[7:0] 0x FF 0x040C DAC full - scale c urrent , Bits[9: 8] 0x01 0x040D Reserv ed 0x00 0x040E Reserv ...

  • Analog Devices AD9912 - page 32

    AD9912 Rev. D | P age 32 of 40 I/O REGISTER DESC RIP TION S SERI AL PORT C ONFIGUR ATION (R EG IS TER 0x 0000 TO REG IST ER 0x 0005) Regist er 0x0000 —Serial P ort Config urat ion Table 13 . Bits B it Name Descript ion [7:4] These b its ar e the mirror imag e of Bit s[3:0 ]. 3 Lo ng i ns truc ti on Rea d - only ; th e AD9912 suppor ts only long i ...

  • Analog Devices AD9912 - page 33

    AD9912 Rev. D | P age 33 of 40 Regist er 0x0011 — Reserved Regist er 0x0012 — Res et ( Autoc learing) To reset t he en tir e chi p , the user c an use the (non - auto cl eari ng) soft r es et bit in Register 0x0000. Table 17 . Bits B it Name Descript ion 0 DDS r eset R eset of the d irect d igital s ynt hes is block. R eset of t his bl ock is v ...

  • Analog Devices AD9912 - page 34

    AD9912 Rev. D | P age 34 of 40 CMOS O UTPUT DIVIDE R (S -DIVIDER) (REG ISTER 0x 0100 TO REG ISTER 0x 0106) Regist er 0x 0100 to Registe r 0x0103 — Reserv ed Regist er 0x0104 —S- Di vider Table 21 . Bits B it Name Descript ion [7:0] S-d ivider CMOS out put divider . Div ide ra tio = 1 − 65,536. If t he des ired S - d ivider s etting is grea te ...

  • Analog Devices AD9912 - page 35

    AD9912 Rev. D | P age 35 of 40 Regist er 0x01A9 — FTW0 ( Fr equen cy T unin g W ord) (Con ti nued) Table 27 . Bit s Bit Name Desc riptio n [31:24] FT W0 These r egist ers conta in the FT W (fr equency tu ning w ord) f or the D DS. The FT W det ermin es the ratio of the A D9912 outpu t frequ ency to it s DA C sys tem c lock. Reg iste r 0x 01 A6 is ...

  • Analog Devices AD9912 - page 36

    AD9912 Rev. D | P age 36 of 40 DOUBLER AND O UTPUT D RIVER S (RE G ISTE R 0x 0200 TO REG IS TE R 0x 0201) Regist er 0x0200 — HSTL Driver Table 32 . Bits B it Name Descript ion 4 OPOL Out put pola rity . Sett ing th is bit inv er ts the HS TL driv er output po larity . [3:2] Reserved Reserved . [ 1: 0] HSTL outp ut d oubler HSTL output doub ler. 0 ...

  • Analog Devices AD9912 - page 37

    AD9912 Rev. D | P age 37 of 40 Regist er 0x0503 — Sp ur A (C ontin ued) Table 38 . Bit s Bit Na me Descr iptio n [7:0] Spur A phase Linear o ffs et fo r Spu r B phas e. Regist er 0x0504 — Sp ur A (C ontin ued) Table 39 . Bits B it Name Descript ion [8] Sp ur A p h as e Linear of fs et for S pur A phase . Regist er 0x0505 — Sp ur B Table 40 . ...

  • Analog Devices AD9912 - page 38

    AD9912 Rev. D | P age 38 of 40 OUTLINE DIMENSIO NS PIN 1 INDI C A T OR T OP VIEW 8. 75 BSC SQ 9.00 BSC SQ 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 BS C 0. 20 RE F 12° M AX 0.80 M AX 0.65 T Y P 1.00 0.85 0.80 7.50 REF 0.05 M AX 0.02 NO M 0.60 M AX 0.60 M AX * 4.85 4.70 S Q 4.55 EXPOSED PAD (BOT TOM VIE W) * COM P L IANT T O JEDEC S T ANDARDS M O ...

  • Analog Devices AD9912 - page 39

    AD9912 Rev. D | P age 39 of 40 ORDERING GUIDE Model T emper atu re Rang e Package De scription P ackage Op tion AD9912A B C PZ 1 , 2 −40°C to +85° C 64 - Lea d Lea d F rame Ch ip Scal e P ackage [ LFCSP_VQ ] CP - 64 -7 AD9912A B C PZ - REEL7 1 , 2 −40°C t o +85°C 64 - Lead L ead F rame Chip Sca le P ackage [LFCSP _VQ] CP - 64 -7 AD9912B CPZ ...

  • Analog Devices AD9912 - page 40

    AD9912 Rev. D | P age 40 of 40 NOTES © 2007 – 2009 Anal og De vice s, Inc. All rights reserved. Tradema rks and registe red trad emarks are the pro perty of their resp ective o wners. D06763 -0- 11/09(D) ...

Manufacturer Analog Devices Category Recording Equipment

Documents that we receive from a manufacturer of a Analog Devices AD9912 can be divided into several groups. They are, among others:
- Analog Devices technical drawings
- AD9912 manuals
- Analog Devices product data sheets
- information booklets
- or energy labels Analog Devices AD9912
All of them are important, but the most important information from the point of view of use of the device are in the user manual Analog Devices AD9912.

A group of documents referred to as user manuals is also divided into more specific types, such as: Installation manuals Analog Devices AD9912, service manual, brief instructions and user manuals Analog Devices AD9912. Depending on your needs, you should look for the document you need. In our website you can view the most popular manual of the product Analog Devices AD9912.

Similar manuals

A complete manual for the device Analog Devices AD9912, how should it look like?
A manual, also referred to as a user manual, or simply "instructions" is a technical document designed to assist in the use Analog Devices AD9912 by users. Manuals are usually written by a technical writer, but in a language understandable to all users of Analog Devices AD9912.

A complete Analog Devices manual, should contain several basic components. Some of them are less important, such as: cover / title page or copyright page. However, the remaining part should provide us with information that is important from the point of view of the user.

1. Preface and tips on how to use the manual Analog Devices AD9912 - At the beginning of each manual we should find clues about how to use the guidelines. It should include information about the location of the Contents of the Analog Devices AD9912, FAQ or common problems, i.e. places that are most often searched by users in each manual
2. Contents - index of all tips concerning the Analog Devices AD9912, that we can find in the current document
3. Tips how to use the basic functions of the device Analog Devices AD9912 - which should help us in our first steps of using Analog Devices AD9912
4. Troubleshooting - systematic sequence of activities that will help us diagnose and subsequently solve the most important problems with Analog Devices AD9912
5. FAQ - Frequently Asked Questions
6. Contact detailsInformation about where to look for contact to the manufacturer/service of Analog Devices AD9912 in a specific country, if it was not possible to solve the problem on our own.

Do you have a question concerning Analog Devices AD9912?

Use the form below

If you did not solve your problem by using a manual Analog Devices AD9912, ask a question using the form below. If a user had a similar problem with Analog Devices AD9912 it is likely that he will want to share the way to solve it.

Copy the text from the picture

Captcha
New picture

Comments (0)