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Cypress CY7C146 - page 1
2K x 8 Dual-Port S t atic RAM CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06031 Rev . *E Revised March 24, 2009 Features ■ T rue dual-ported memory cells that enable simultaneous reads of the same memory loca tion ■ 2K x 8 orga ...
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Cypress CY7C146 - page 2
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 2 of 15 Pinout s Figure 1. 52-Pin PLCC (T op View) Figure 2. 52-Pin PQFP (T op View) Selection Guide Specificati on 7C136-15 [4] 7C146-15 7C132-25 [4] 7C136-25 7C142-25 7C146-25 7C132-30 7C136-30 7C142-30 7C146-30 7C132-35 7C136-35 7C142-35 7C146-35 7C132-45 7C136-45 7C1 ...
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Cypress CY7C146 - page 3
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 3 of 15 Maximum Ratings Exceeding maximum ratin gs may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature .......... ......... ........... ....... − 65°C to +150°C Ambient T empe rature w ith Power Applied . ........... ...
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Cypress CY7C146 - page 4
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 4 of 15 Cap acit ance This parameter is guaranteed but not tested. Parameter Description T e st Conditio ns Max Unit C IN Input Capacit ance T A = 25 ° C, f = 1 MHz, V CC = 5.0V 1 5 p F C OUT Output Capacit a nce 10 pF Figure 3. AC T est Lo ads and Waveforms 3.0V 5V OUT ...
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Cypress CY7C146 - page 5
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 5 of 15 Write Cycle [12] t WC Wri te Cy cl e Ti me 15 25 30 ns t SCE CE LOW to Write End 12 20 25 ns t AW Address Setup to Write End 12 20 25 ns t HA Address Hold from Write End 2 22 n s t SA Address Setup to Write S tart 0 00 n s t PWE R/W Pulse Width 12 15 25 ns t SD D ...
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Cypress CY7C146 - page 6
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 6 of 15 Switching Characteristics Over the Operating Range (S peeds -35, -45, -55) [8] Parameter Description 7C132-35 7C136-35 7C142-35 7C146-35 7C132-45 7C136-45 7C142-45 7C146-45 7C132-55 7C136-55 7C136A-55 7C142-55 7C146-55 Unit Min Max Min Max Min Max Read Cycle t RC ...
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Cypress CY7C146 - page 7
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 7 of 15 Interrupt Timing [16] t WINS R/W to INTERRUPT Set T ime 25 35 45 ns t EINS CE to INTERRUPT Set Time 25 35 45 ns t INS Address to INTERRUPT Set T ime 25 35 45 ns t OINR OE to INTERRUPT Reset T ime [13] 25 35 45 ns t EINR CE to INTERRUP T Reset Time [13] 25 35 45 n ...
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Cypress CY7C146 - page 8
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 8 of 15 Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 an d CY7C136/CY7C136A) Figure 7. Write Cycle No.1 (O E Three-St ates Data I /Os—Either Port) [12, 20] Switching W aveforms (continued) t BHA t BDD VA L I D t DDD t WDD ADDRESS MA TCH ADDRESS MA TCH R/W ...
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Cypress CY7C146 - page 9
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 9 of 15 Figure 8. Write Cycle No. 2 (R/W Three-St ates Dat a I/Os—Eithe r Port) [12, 21] Figure 9. Busy Timing Diagram No. 1 (CE Arbitration) Switching W aveforms (continued) t AW t WC t SCE t SA t PWE t HD t SD t HZWE t HA HIGH IMPEDANCE CE R/W ADDRESS D OUT DA T A IN ...
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Cypress CY7C146 - page 10
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 10 of 15 Figure 10. Busy Timing Diagra m No. 2 (Address Arbitration) Figure 1 1. Busy Timing Diagram No. 3 (Write with BUSY , Slave: CY7C142/CY7C146) Switching W aveforms (continued) Lef t Address V alid First: ADDRESS MA TCH t PS ADDRESS L BUSY R ADDRESS MISMA TCH t RC ...
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Cypress CY7C146 - page 11
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 1 1 of 15 Interrupt Timing Diagrams [16] Figure 12. Left Side Sets INT R Figure 13. Right Side Clears INT R Figure 14. Right Side Set s INT L Figure 15. Right Side Clea rs INT L Switching W aveforms (continued) WRITE 7FF t INS ADDRESS L R/ W L t WC t EINS CE L t HA t SA ...
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Cypress CY7C146 - page 12
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 12 of 15 Figure 16. T ypical DC and AC Characteris tics 1.4 1.0 0.4 4.0 4.5 5.0 5.5 6.0 –55 25 125 1.2 1.0 120 100 80 60 40 20 0 1.0 2.0 3.0 4.0 OUTPUT SOURCE CURRENT (mA) SUPPL Y VOL T AGE (V) NORMALIZED SUPPL Y CURRENT vs. SUPPL Y VOL T AGE NORMALIZED SUPPL Y CURRENT ...
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Cypress CY7C146 - page 13
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 13 of 15 Ordering Information Spe ed (ns) Ordering C ode Package Diagram Package T ype Operating Range 15 CY7C136-15JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial CY7C136-15NC 51-85042 52-Pin Plastic Quad Flatpack 25 CY7C136-25JC 51-85004 52-Pin Plastic Leaded ...
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Cypress CY7C146 - page 14
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev . *E Page 14 of 15 Package Diagrams Figure 17. 52-Pin Plastic Leaded Chip Carrier , 51-85004 Figure 18. 52-Pin Plastic Quad Flatpack, 51-85042 51-85004-*A 51-85042-** [+] Feedback ...
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Cypress CY7C146 - page 15
Document #: 38-06031 Rev . *E Revised March 24, 2009 Page 15 of 15 All product s and company name s mentioned in this docum ent may be the trademar ks of their respective holders. CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 © Cypress Sem iconductor Corp oration, 2005-2009. The informatio n contai ned herein is su bject to chan ge without no tice. ...
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