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Cypress CY7C1414JV18 - page 1
36-Mbit QDR™-II SRAM 2-W ord Burst Architecture CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-12561 Rev . *D Revised March 10, 2007 Features ■ Separate independent read and write data ports ❐ Supports concurrent tran ...
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Cypress CY7C1414JV18 - page 2
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 2 of 26 Logic Block Diagram (CY7C1410JV18) Logic Block Diagram (CY7C1425JV18) 2M x 8 Array CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 8 21 16 8 NWS [1:0] V ...
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Cypress CY7C1414JV18 - page 3
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 3 of 26 Logic Block Diagram (CY7C1412JV18) Logic Block Diagram (CY7C1414JV18) 1M x 18 Array CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. RPS WPS Control Logic Address Register Reg. Reg. Reg. 18 20 36 18 BWS [1:0 ...
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Cypress CY7C1414JV18 - page 4
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 4 of 26 Pin Configuration The pin configuration for CY7C1410JV18, CY7C1412 JV18, and CY7C1414JV18 follow . [1] 165-Ball FBGA (15 x 17 x 1 .4 mm) Pinout CY7C1410JV18 (4M x 8) 123456789 1 0 1 1 A CQ NC/72M A WPS NWS 1 K NC/144M RPS AA C Q B NC NC NC A NC/288M K ...
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Cypress CY7C1414JV18 - page 5
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 5 of 26 CY7C1412JV18 (2 M x 18) 123456789 1 0 1 1 A CQ NC/144M A WPS BWS 1 K NC/288M RPS A NC/72M CQ B NC Q9 D9 A NC K BWS 0 AN C N C Q 8 C NC NC D10 V SS AAA V SS NC Q7 D8 D NC D1 1 Q1 0 V SS V SS V SS V SS V SS NC NC D7 E NC NC Q1 1 V DDQ V SS V SS V SS V DD ...
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Cypress CY7C1414JV18 - page 6
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 6 of 26 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during val id write opera tions. CY7C1410JV18 - D [7:0] CY7C1425JV18 - D [8:0] CY7C1412JV18 - D [17:0] CY7C1414JV18 ...
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Cypress CY7C1414JV18 - page 7
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 7 of 26 CQ Echo Clock CQ is Referenced with Respec t to C . This is a free - running clock and is synchronized to the Input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks is ...
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Cypress CY7C1414JV18 - page 8
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 8 of 26 Functional Overview The CY7C1410JV18, CY7C142 5JV18, CY7C1412JV18, and CY7C1414JV18 are synchronous pipel ined Burst SRAMs with a read port and a write port. The read port is dedicated to rea d operations and the write port is dedicated to write operat ...
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Cypress CY7C1414JV18 - page 9
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 9 of 26 Programmable Impedan ce An external resistor , RQ, must be connected between the ZQ pin on the SRAM and V SS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of th e intended line impedance d riven by the SR ...
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Cypress CY7C1414JV18 - page 10
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 10 of 26 T ruth T able The truth table for CY7C1410JV18, CY7C1425JV 18, CY7C1412JV18, and CY7C1414JV18 fo llows. [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ Write Cycle: Load address on the rising ed ge of K ; input write data on K and K rising edges. L-H X L ...
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Cypress CY7C1414JV18 - page 11
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 1 1 of 26 Write Cycle Descriptions The write cycle description tabl e for CY7C1425JV18 follows. [2, 8] BWS 0 K K Comments L L–H – During the Data portion of a write sequence, the single byte (D [8:0] ) is writ te n in to the device. L – L–H Du ring the ...
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Cypress CY7C1414JV18 - page 12
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 12 of 26 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.1-2001. The T AP operates using JEDEC standard 1.8V IO log ...
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Cypress CY7C1414JV18 - page 13
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 13 of 26 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It also places the instru ction register between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters the Shif ...
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Cypress CY7C1414JV18 - page 14
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 14 of 26 T AP Controller St ate Diagram The state diagram for the T AP controller follows. [9] TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 ...
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Cypress CY7C1414JV18 - page 15
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 15 of 26 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 μ A1 ...
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Cypress CY7C1414JV18 - page 16
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 16 of 26 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Setup to ...
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Cypress CY7C1414JV18 - page 17
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 17 of 26 Identification R egi ster Definitions Instruction Field Va l u e Descriptio n CY7C1410JV18 CY7C1425JV18 CY7C1 412JV18 CY7C1414JV18 Revision Numb er (31:29) 001 001 001 001 V ersion number . Cypress Device ID (28:12) 1 1 01001 10100001 1 1 1 101001 101 ...
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Cypress CY7C1414JV18 - page 18
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 18 of 26 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6 P2 9 9 G 5 7 5 B8 5 2 J 2 6N 30 1 1F 58 5A 86 3K 3 7P 31 1 1G 59 4A 87 3J 4 7 N3 2 9 F 6 0 5 C8 8 2 K 5 7R 33 10F 61 4B 89 1K 6 8R 34 1 1E 62 3A 90 ...
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Cypress CY7C1414JV18 - page 19
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 19 of 26 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of st able clock. Power Up Seq ...
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Cypress CY7C1414JV18 - page 20
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 20 of 26 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature .......... ................. ...... –65°C to +150°C Ambient T empe r at ur e with Power Applied.... ...
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Cypress CY7C1414JV18 - page 21
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 21 of 26 AC Electrical Characteristics Over the Operating Range [1 1] Parameter Description T est Conditio ns Min Ty p Max Unit V IH Input HIGH V oltage V REF + 0.2 – – V V IL Input LOW V oltage – – V REF – 0.2 V Cap acit ance T ested initially and a ...
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Cypress CY7C1414JV18 - page 22
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 22 of 26 Switching Characteristics Over the Operating Range [19, 20] Cypress Parameter Consor tium Parameter Description 26 7 MHz 250 MHz Unit Min Max Min Max t POWER V DD (T ypical) to the first access [21] 11 m s t CYC t KHKH K Clock and C Clock Cycle Time 3 ...
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Cypress CY7C1414JV18 - page 23
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 23 of 26 Switching W aveforms Figure 3. Read/Write/Deselect Sequence [2 5, 26, 27 ] K 1 2 34 5 8 10 6 7 K RPS WPS A D READ READ WRITE WRITE WRITE NOP READ WRITE NOP 9 A0 t KH t KHKH t KL t CY C tt HC t SA t HA t SD t HD SC t t SA t HA t SD t HD A6 A5 A3 A4 A1 ...
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Cypress CY7C1414JV18 - page 24
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 24 of 26 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Code Package Diagram Package T ype Op ...
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Cypress CY7C1414JV18 - page 25
CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 Document #: 001-12561 Rev . *D Page 25 of 26 Package Diagram Figure 4. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35±0.06 1.40 MAX. SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP ...
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Cypress CY7C1414JV18 - page 26
Document #: 001-12561 Rev . *D Revised March 10, 2007 Page 26 of 26 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s developed by Cypress, I DT , NEC, R enesas, and Sa msung. All pr oduct and comp any names mentioned i n this documen t are the tr ad emarks of their respe ctive hold er s. CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, ...
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