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Toshiba Semiconductor - page 1
[6] Handling Guide 93 [ 6 ] Handling Guide 1. Using T oshiba Semiconductors Safely TOSH IBA is contin ually wo rking to improve t he qu ality and reliabi lity of its produc ts. Neverthe less, semicondu cto r devices in ge neral can mal f unction o r fai l due to their i nherent el ectrical sensitiv ity and vul nerability t o physical stress. It is ...
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Toshiba Semiconductor - page 2
[6] Handling Guide 94 2. Safety Precautions This section lists imp ortant precaut ions whic h users of semiconduct or devic es (and an yone els e) should ob serve in or der t o avoid i njury and damag e to prop erty , and to ensur e safe a nd cor rect use of devices . Please be sur e that you underst and the meaning s of the labels and the gr aphic ...
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Toshiba Semiconductor - page 3
[6] Handling Guide 95 2.1 General Precautions reg arding Semiconductor D evices Do not use devices under conditions exceeding t hei r absolut e maxim um ratings (e. g. c urrent, vol t age, pow er dissi pation or temperature). This may cause the device to break down, degrade its performance, or caus e it to catch fire or explode resulti ng in inj ur ...
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Toshiba Semiconductor - page 4
[6] Handling Guide 96 3. General Safety Precautions and Usage Considerations This secti on is designed to help you gain a better understandi ng of semico n ductor devices , so as to ensure the s afety , qualit y and relia bility of the devic es which you inc orporate into your designs. 3.1 From Incoming to Shipping 3.1.1 Elect rostatic Discharge (E ...
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Toshiba Semiconductor - page 5
[6] Handling Guide 97 (e) Make s ure that se ctions of the ta pe carrier wh i ch come i nto contact wi th install a tion device s or other elect rical mach inery are mad e of a l ow-resist ance mat erial. (f) Make sure that jigs and tools used in the assembly process do not touch devic es. (g) I n processe s in which packa ge s may retai n an elect ...
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Toshiba Semiconductor - page 6
[6] Handling Guide 98 • Whe n storing pri n ted circuit boards wh ich have device s mounted on them, use a board container or bag that is prot ected ag ainst stat ic charge. T o avoid the occ urrence of stati c charge or discharg e due t o fri ction, keep the b oards sep arat e from one other and do not stack them direc tly on top of one anot h e ...
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Toshiba Semiconductor - page 7
[6] Handling Guide 99 3.2 Sto rage 3.2.1 Gen eral Storage • A void storage l o cations wher e device s will b e exposed to moistur e or dir ect sunlig ht • Follow the instructions pri nted on the device cartons regarding transport ation and st orage. • The storag e area t emperatur e should be kept with in a temperature r ange of 5°C to 35° ...
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Toshiba Semiconductor - page 8
[6] Handling Guide 100 3.3 Design Care must be exer cised in the des i gn of elect ronic e quipm ent to ach ieve t he desir ed rel iability . It is important n ot only to adhere to specif ications c oncerning absolut e maximu m ratings and recommend ed oper ating condit ions, it is also imp ortant to consid er the ov erall envir onment i n which eq ...
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Toshiba Semiconductor - page 9
[6] Handling Guide 101 3.3.4 Input processing Inputs to CMO S ICs hav e such a high i m pedance that the log ic level b e comes undef ined under open i nput conditions. S hould t he float ing input be neith er High nor Low , both P-cha nnel and N-c hannel tr ansistors tu rn on, and unnece ssary supply cu rre nt flows. Therefor e, as shown in Fig ur ...
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Toshiba Semiconductor - page 10
[6] Handling Guide 102 3.3.7 Effe ct of Slow Rise and Fall Time on Input When a wav eform wit h a slow rise and fall time is applie d to a CMOS input, th e output will sometimes tend to oscillate around V th (the circuit thres hold voltage) of th e input waveform. This is becau se the CMOS gate becomes an eq uivalen t linear ampli fier in the vi ci ...
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Toshiba Semiconductor - page 11
[6] Handling Guide 103 3.3.10 Wirin g Precaut ions (1) Output waveform distortion Since the output i mpedanc es of t he Mini- MOS Ser ies are v ery low , distor tion is s ometim es caused in the outp ut wavef orm by the L componen t of th e wiring . This oc curs when t he wiring connected to the output pin i s long or w hen capac itance is c onnect ...
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Toshiba Semiconductor - page 12
[6] Handling Guide 104 3.3.11 Latch-up CMOS dev ices are subj ect to latch-up , an undes irable co ndit ion in whic h a paras itic P NPN junc tion (thyristo r) in the CMOS I C co nducts. An abnormal current of se veral hundred m A can flow be tween V CC and GND, destroying th e IC. Latch-up occurs when th e voltag e applied t o the input or out put ...
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Toshiba Semiconductor - page 13
[6] Handling Guide 105 T able 3.1 T est Resu lt EIAJ Method MIL-STD Method Name Input Output Input Out put TC7MH244FK >± 200 V >± 200 V >± 2000 V >± 2000 V TC7MET244AFK >± 200 V >± 200 V >± 2000 V >± 2000 V TC7MZ244FK >± 200 V >± 200 V >± 2000 V >± 2000 V TC7MA244FK >± 200 V >± 200 V >± 20 ...
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Toshiba Semiconductor - page 14
[6] Handling Guide 106 3.3.13 M eta-St able Characteristi cs When the s etup t ime or hold-t ime of a f lip-fl op is not ad hered to th e device’ s output respons e is uncertain. T his ph enomenon is called meta-st abilit y . The dia gram shown above describ es a meta-sta ble state which can gene rate a glitch or increa se the propaga tion delay ...
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Toshiba Semiconductor - page 15
[6] Handling Guide 107 3.3.14 T hermal Design The fail ure rate o f semicond ucto r devices is greatl y increased a s operatin g temperatu r e s increa se . As shown in Figure 3.9, the i nternal thermal st ress on a devic e is the sum of the ambient temperature and the t emperatur e rise due to pow er dissip ation in the d e vice. Therefor e, to ac ...
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Toshiba Semiconductor - page 16
[6] Handling Guide 108 3.3.16 External No ise Printed circ uit boards w ith long I/O or sign al patt ern lines are vulnerab le to induc ed noise or surg es from outsid e sources. Consequently , malfunctions or breakdowns can r esult from overcur rent or ov ervo ltage, d epending on the t ypes of d evi ce used. T o protect aga inst nois e, lower the ...
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Toshiba Semiconductor - page 17
[6] Handling Guide 109 3.3.19 Safety Stan dards Each countr y has safety standar ds which must be obs erved. Thes e safety standards include requirement s for qu ality a ssurance sy stems and design of device insulatio n. Such requ irement s must be fully t aken into account to ensure that your d esign conf orms to th e applic able safet y standar ...
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Toshiba Semiconductor - page 18
[6] Handling Guide 110 3.4.2 Inspect ion Sequence 1. Do not inser t devic es in the wrong or ientation. Make su re that the positiv e and neg ative el ectrodes of the p ower supply are c orrectly conne cted. Othe rwise, the rated ma ximum curre nt or maximu m power dissipat ion may b e exce eded and the dev ice may br eak do wn or under go perform ...
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Toshiba Semiconductor - page 19
[6] Handling Guide 111 on the internal lea d s. I f the relative di ffere nce is grea t enough, the device’ s interna l leads, adh esive proper ties or s ealant can be damaged. O bserv e these p recaution s during the l ead-form ing p rocess (this does n ot apply to surfac e-mount devices): (1) Lead inser tion h ole interva ls on the p rint ed ci ...
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Toshiba Semiconductor - page 20
[6] Handling Guide 112 3.5.3 Solder ing T emp erature Pr ofile The solder ing t emperat ure and heating time var y from d evice t o devic e. Therefor e, when specify ing the mounting conditions, re fer to the individual datasheets and da tabooks for the devices used. (1) Using a sold ering iron Complet e solder ing within t en seconds for lead temp ...
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Toshiba Semiconductor - page 21
[6] Handling Guide 113 3.5.4 Flux Cleaning and Ultra sonic Cleaning (1) Whe n cleaning ci rcuit boards to re move flux, ma ke sure that no res idual rea cti ve ions such as Na or Cl rema i n. Note that organi c solvents rea ct with water to ge nerate hydro gen chloride a nd other co rrosive ga se s which can degra de device perfo rmance. (2) W ashi ...
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Toshiba Semiconductor - page 22
[6] Handling Guide 114 3.5.5 No Clean ing If analo g devices or hi gh-speed devices are used wi tho u t being clea n ed, flux residue s may cause minute amounts of leakage between pins. Simi larly , dew condensati on, which oc curs in env ironments contai ning resi dual chlori ne when powe r to the device is on, ma y cause betwe en-lead leaka ge or ...
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Toshiba Semiconductor - page 23
[6] Handling Guide 115 3.6 Protecting Devices in the Field 3.6.1 T emperat ure Semi co nductor devi ces are gen e rally mo re sensiti ve to temperature than are oth e r electroni c component s. The v arious elect rical char acteristic s of a semiconduc tor devic e are d ependent on the ambient te mperatur e at w hich t he devic e is used . It is th ...
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Toshiba Semiconductor - page 24
[6] Handling Guide 116 3.6.6 Interferen ce from L ight (ult raviolet ra ys, sunligh t, fluo rescent lamps and incan descent lamps) Light stri king a semi conductor de vice genera tes electro motive force due to photoelectri c effects. In some ca se s the device can malfuncti on. This is especially true for devices in which the inte rnal ch i p is e ...
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