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Manual Cypress CY7C1381D

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  • Cypress CY7C1381D - page 1

    18-Mbit (512K x 36/1M x 18) Flow-Through SRAM CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Cypress Semiconductor Co rporation • 198 Champio n Court • San Jose , CA 95134-1 709 • 408-943-2600 Document #: 38-05544 Rev . *F Revised Feburary 07, 2007 Features • Supports 133 MHz bus operations • 512K × 36 and 1M × 18 common IO • 3.3V core pow ...

  • Cypress CY7C1381D - page 2

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 2 of 29 Logic Block Diagram – CY7C1381D/CY7C138 1F [3] (512K x 36) Logic Block Diagram – CY7C1383D/CY7C138 3F [3] (1M x 18) ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE A [1:0] DQs DQP A ...

  • Cypress CY7C1381D - page 3

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 3 of 29 Pin Configurations A A A A A 1 A 0 NC NC V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQ C V DDQ V SSQ DQ C DQ C DQ C ...

  • Cypress CY7C1381D - page 4

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 4 of 29 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R T U V DDQ NC/288M NC/144M DQP C DQ C DQ D DQ C DQ D AA A A ADSP V DDQ AA DQ C V DDQ DQ C V DDQ V DDQ V DDQ DQ D DQ D NC NC V DDQ V DD CLK V DD V SS V SS V SS V SS V SS V SS V SS V SS NC/576M NC ...

  • Cypress CY7C1381D - page 5

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 5 of 29 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1381D (512K x 36) 234 567 1 A B C D E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE 2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D DQ D NC/36M NC/7 ...

  • Cypress CY7C1381D - page 6

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 6 of 29 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address inputs used to select one o f the address location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , an d CE 1 , CE 2 , and CE 3 [2] are sampled active. A [1:0] feed ...

  • Cypress CY7C1381D - page 7

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 7 of 29 Functional Overview All synchronous inpu ts pass through input registers controlled by the rising edge of the clock. Maximum a ccess delay from the clock rise (t CDV ) is 6.5 ns (133 MHz device). The CY7C1381D/CY 7C1383D/CY7C1381F/CY7C1383F supports secondary cache ...

  • Cypress CY7C1381D - page 8

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 8 of 29 deasserted and the IOs must be tri-stated prior to the presen- tation of data to DQs. As a safe ty precaution, the data lines a re tri-stated once a write cycle is det ected, regardle ss of the state of OE . Single Write Accesses Initiated by AD S C This write acce ...

  • Cypress CY7C1381D - page 9

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 9 of 29 T ruth T able [4, 5, 6, 7, 8] Cycle Description ADDRESS Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power Down None H X X L X L X X X L-H T ri-S tate Deselected Cycle, Power Down None L L X L L X X X X L-H T ri-S tate Deselected Cycle, Po ...

  • Cypress CY7C1381D - page 10

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 10 of 29 T ruth T able for Read/Write [4, 9] Function (CY7C1381D/CY7C1381F) GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte A (DQ A , DQP A ) H L HHH L Write Byte B(DQ B , DQP B )H L H H L H Write Bytes A, B (DQ A , DQ B , DQP A , DQP B )H L H H L L ...

  • Cypress CY7C1381D - page 11

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 1 1 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1381D/CY 7C1383D/CY7C1381F/CY7C1383F incorporates a serial boun dary scan test access port (T AP).This part is fully compliant with 1 149.1. The T AP operates using JEDEC-standard 3.3V or 2.5V IO logic levels. The ...

  • Cypress CY7C1381D - page 12

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 12 of 29 Byp ass Register T o save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed betwee n the TDI and TDO balls. This allows data to be shifted through ...

  • Cypress CY7C1381D - page 13

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 13 of 29 (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will en able the output bu ffers to drive the output bus. When LOW , this bit will place the output bus into a High-Z condition. This bit can be set by enterin g the SAMPLE/PRELOAD ...

  • Cypress CY7C1381D - page 14

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 14 of 29 3.3V T AP AC T est Conditions Input pulse levels ............. .............. .............. ........V SS to 3.3V Input rise and fall times ............ ............ ........... ................ 1 ns Input timing reference levels .................. ............... ...

  • Cypress CY7C1381D - page 15

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 15 of 29 Identification Register Definitions Instruction Field CY7C1381D/CY7C1381F (512K × 36) CY7C1383D/CY7C1383F (1M × 18) Description Revision Number (31:29) 000 000 Describes the version numb er . Device Depth (28:24) [13] 01 01 1 0101 1 Reserved for internal use . D ...

  • Cypress CY7C1381D - page 16

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 16 of 29 1 19-Ball BGA Boundary Scan Order [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 G4 67 L1 2 T 42 4 E 74 6 A 46 8 M 2 3T 5 2 5 D 7 4 7 G 3 6 9 N 1 4 T 6 2 6 H 74 8 C 37 0 P 1 5R 5 2 7 G 6 4 9 B 2 7 1 K 1 6 L 5 2 8 E 65 0 B 37 2 L 2 7 ...

  • Cypress CY7C1381D - page 17

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 17 of 29 165-Ball BGA Boundary Scan Order [14, 16] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2N 7 3 2 C 1 1 6 2 D 2 3 N10 33 A1 1 63 E2 4P 1 1 3 4 B 1 1 6 4 F 2 5 P 8 35 A10 65 G2 6 R8 36 B10 66 H1 7R 9 3 7 A 9 6 7 H 3 8P 9 3 8 B 9 6 8 J 1 9P 1 0 3 9 C 1 ...

  • Cypress CY7C1381D - page 18

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 18 of 29 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. For user guideline s, not tested. S torage T emperature .............. .............. ..... –65°C to +150°C Ambient T emperatur e with Power Applied ....................... ...

  • Cypress CY7C1381D - page 19

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 19 of 29 Cap acit ance [19] Parameter Description T est Con ditions 100 TQFP Package 1 19 BGA Package 165 FBGA Package Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V . V DDQ = 2.5V 589 p F C CLK Clock Input Capacitance 5 8 9 pF C IO Input/Output Capacitanc ...

  • Cypress CY7C1381D - page 20

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 20 of 29 Switching Characteristics Over the Operating Range [20, 21] Parameter D escription 133 MHz 100 MHz Unit Min Max Min Max t POWER V DD (T ypical) to the first Access [22] 11 m s Clock t CYC Clock Cycle Ti me 7.5 10 ns t CH Clock HIGH 2.1 2.5 ns t CL Clock LOW 2.1 2. ...

  • Cypress CY7C1381D - page 21

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 21 of 29 Ti ming Diagrams Read Cycle Timing [26] t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES Data Out (Q) High-Z t CLZ t DOH t CDV t OEHZ t CDV Single READ BURST READ t OEV t OELZ t CHZ Burst wraps around to its initial state t ADVH t ADVS t WEH t WES ...

  • Cypress CY7C1381D - page 22

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 22 of 29 Write Cycle T iming [26, 27] Ti ming Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3) A2 A3 Extended BURST WRITE D(A2 + 2) Single ...

  • Cypress CY7C1381D - page 23

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 23 of 29 Read/Write Cycle Timing [26, 28, 29] Ti ming Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A2 t CEH t CES Single WRITE D(A3) A3 A4 BURST READ Back-to-Back READs High-Z Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) t WEH t WES t OEHZ t DH t DS t CDV ...

  • Cypress CY7C1381D - page 24

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 24 of 29 ZZ Mode T iming [30, 31] Ti ming Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes: 30. Device must be deselected when enterin g ZZ mode. See T ruth T able [4, 5 ...

  • Cypress CY7C1381D - page 25

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 25 of 29 Ordering Information Not all of the speed, package and temperatu re ranges are ava ilable. Please contact your local sales representative or visit www .cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram Part and Packa ge T ype Opera ...

  • Cypress CY7C1381D - page 26

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 26 of 29 Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3 ...

  • Cypress CY7C1381D - page 27

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 27 of 29 Figure 2. 1 19-ball BGA (14 x 22 x 2.4 mm) (51-851 1 5) Package Diagrams (continued) 51-851 15-*B [+] Feedback ...

  • Cypress CY7C1381D - page 28

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 28 of 29 © Cypress Semicon ductor Corpor ation, 2006-20 07. The informat ion conta ined herein is sub ject to change withou t notice. Cypress Semiconductor Corp oration assumes no responsibility for the use of any circuitr y other than circuitry emb odied in a Cypress pro ...

  • Cypress CY7C1381D - page 29

    CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Document #: 38-05544 Rev . *F Page 29 of 29 Document History Page Document Title: CY7C1381D/CY7C1383D/CY7C1381F/CY7C138 3F 18-Mbit (51 2K x 36/1M x 18) Flow-Through SRAM Document Number: 38-05544 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 254518 See ECN RKF New data sheet *A 288531 Se ...

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All of them are important, but the most important information from the point of view of use of the device are in the user manual Cypress CY7C1381D.

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